中文 English

Minimizing EM/IR Impacts On IC Design Reliability And Performance


By Joel Mercier and Karen Chow As technologies and foundry process nodes continue to advance, it gets more difficult to design and verify integrated circuits (ICs). The challenges become even more apparent in 5nm and below nodes, and as the industry moves away from fin field-effect transistor (finFET) and into gate-all-around field-effect transistor (GAAFET) technologies. There are many prob... » read more

ESD P2P And CD Verification Doesn’t Have To Be Hard


As a designer or verification engineer, you’re fighting the effects of electrostatic discharge (ESD) in your integrated circuit (IC) designs all the time. ESD is one of those frustrating issues that can challenge even the most experienced designers. Once an IC is in the market, unexpected electrical shorts will cause immediate failure or dielectric breakdown will result in gradual circuit deg... » read more

How FinFET Device Performance Is Affected By Epitaxial Process Variations


By Shih-Hao (Jacky) Huang and Yu De Chen As the need to scale transistors to ever-smaller sizes continues to press on technology designers, the impact of parasitic resistance and capacitance can approach or even outpace other aspects of transistor performance, such as fringing capacitance or source drain resistance. The total resistance in a device is comprised of two components: internal re... » read more

Fins And Wires – How Do We Get To 5nm?


As the industry moves beyond 10nm to the 7nm and 5nm nodes, fundamental shifts are needed to address scaling challenges. Among the priority concerns driving industry changes, particularly with respect to materials and architecture, is the impact on transistor performance from rising parasitic resistance and parasitic capacitance or RC. I spoke about this industry dilemma recently at the SEMICON... » read more