tag: physical layer

The Evolution Of UCIe
By Ed Sperling - 02 Jun, 2026 - Comments: 0

Since it was released in March 2022, the Universal Chiplet Interconnect Express (UCIe) has grown from a basic way of connecting two dies together into a comprehensive specification that can ensure the handoff of data between various components in an advanced package, as well as validate the chiplets within that package. Mayank Bhatnagar, director of product marketing at Cadence, talks about the... » read more

Exploring The Latest Innovations In MIPI D-PHY And MIPI C-PHY
By Michael Nagib - 15 Jan, 2026 - Comments: 0

By Michael Nagib and Nuno Martins In the ever-evolving landscape of high-performance camera and display technologies, MIPI D-PHY and MIPI C-PHY specifications continue to lead the charge, setting benchmarks for low power, low latency, and high bandwidth data transmission. Building on the insights from our previous article, “Demystifying MIPI C-PHY/D–PHY Subsystem” – we now delve into... » read more

Often Overlooked, PHYs Are Essential To High-Speed Data Movement
By Ann Mutschler - 17 Jul, 2025 - Comments: 0

Over the past couple of decades, the semiconductor industry has evolved from a supporting role for traditional verticals like mobile, automotive, and PCs to a foundational role in those markets, as well as in AI factories and hyperscale data centers. Underlying this transformation is the physical layer (PHY), which has emerged as a critical enabler for data transfer and communications. The P... » read more

Where Power Is Spent In HBM
By Ed Sperling - 06 Feb, 2023 - Comments: 0

HBM is gaining ground because of a spike in the amount of data that needs to be processed quickly, but big reductions in power are possible if that processing can be moved closer to the HBM modules, and if more can be done in each compute cycle without sending data back and forth to memory as frequently. Steven Woo, fellow and distinguished engineer at Rambus, talks about what can be done to bo... » read more

UCIe: Marketing Ruins It Again
By Brian Bailey - 24 Mar, 2022 - Comments: 1

You may have seen the press release and articles recently about a new standard called UCIe. It stands for Universal Chiplet Interconnect Express. The standard is a great idea and will certainly help the market for chiplet-based designs to advance. But the name — Argggh. More on that later. First, let's talk about what it is. You may notice the name looks similar to PCIe (Peripheral Compone... » read more

Architecting Interposers
By Brian Bailey - 14 Oct, 2021 - Comments: 0

An interposer performs a similar function as a printed circuit board (PCB), but when the interposer is moved inside a package the impact is significant. Neither legacy PCB nor IC design tools can fully perform the necessary design and analysis tasks. But perhaps even more important, adding an interposer to a design may require organizational changes. Today, leading-edge companies have shown ... » read more

Power Impact At The Physical Layer Causes Downstream Effects
By Ann Mutschler - 09 Jul, 2020 - Comments: 0

Data movement is rapidly emerging as one of the top design challenges, and it is being complicated by new chip architectures and physical effects caused by increasing density at advanced nodes and in multi-chip systems. Until the introduction of the latest revs of high-bandwidth memory, as well as GDDR6, memory was considered the next big bottleneck. But other compute bottlenecks have been e... » read more

A Primer For The 802.XX Physical Layer
By Ernest Worthman - 07 Oct, 2015 - Comments: 0

This is the second installment of the 802.XX for the IoE series of articles. The first one was published in the August issue and addressed the Media Access Control (MAC) layer. In this article, we will examine the elements of the physical (PHY) layer of the 802.11 protocol stack. For reference, the protocol stack is shown in figure 1. The best designs, like everything else, are built on a so... » read more

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