Waking And Sleeping Create Current Transients

Silicon power-saving techniques are helping to reduce the power required by data centers and other high-intensity computing environments, but they’ve also added a significant challenge for design teams. As islands on high-powered chips go to sleep and wake up, the current requirements change quickly. This happens in a few microseconds, at most. The rapid change of loading creates a challen... » read more

Thermal Issues Getting Worse

Making sure that smartphone you’re holding doesn’t burn your face when you make a call requires a tremendous amount of engineering effort at all levels of the design - the case, the chips, the packaging. The developers of the IP subsystems in that smartphone must adhere to very strict power and energy thresholds so the OEM putting it all together can stick to some semblance of a product des... » read more

All Things To All Customers

By Ann Steffora Mutschler Low-Power High-Performance Engineering recently spoke with Suresh Menon, VP of systems development at Lattice Semiconductor, about the challenges of directing the development of power-sensitive FPGAs from architectural decisions to identifying the target applications. What follows are excerpts of that discussion. LPHP: When you look at the products that Lattic... » read more