tag: power modeling

Why Power Modeling Is So Difficult
By Ed Sperling - 15 Feb, 2016 - Comments: 2

Power modeling has been talked about for years and promoted by EDA vendors and chipmakers as an increasingly important tool for advanced designs. But unlike hardware and software modeling, which have been proven to speed time to market for multiple generations of silicon, power modeling has some unique problems that are more difficult to solve. Despite continued development in this field, po... » read more

Shift In Focus For Low Power Design
By Alan Gibbons - 10 Sep, 2015 - Comments: 0

The increased levels of interest we have seen over the last couple of years in system-level power modeling and energy-aware system-level design methodology, coupled with broad participation in the associated industry standard activities around system level power, gives us a clear indication that a shift in focus for low-power design is taking place. Our attempts to deliver energy-efficient high... » read more

What To Do With Power Models
By Ann Mutschler - 13 Aug, 2015 - Comments: 0

Ask any design engineer if they want a power model, and you can guess the answer. As far as what they want to use it for, the answer will vary. When I asked Jem Davies, ARM Fellow, if OEM engineering teams want a comprehensive power model, he said, “Ideally, yes. Perfectly ideally, what they would like to have from us is a model of each individual block of our IP which plugs together in a ... » read more

Extending UPF For Use In System-Level Design
By Alan Gibbons - 12 Mar, 2015 - Comments: 0

Energy efficiency as a design constraint continues to dominate, and now that we see greater momentum behind a shift left toward system-level design, we are naturally seeing power-aware system-level design as a key area for EDA and IP enablement, especially among mobile and IoT platform providers. In my last article I highlighted the role that IP power models play in the architecture and design ... » read more

Designing In The Dark
By Jon McDonald - 25 Sep, 2014 - Comments: 0

While power optimization has received significant focus recently, it is still largely a hidden cost to most hardware and software engineers. A significant problem is the lack of visibility into the impact of decisions while decisions are being made. Often an engineer working on a system will have no practical way of measuring the impact of their design decisions on the system power consumption.... » read more

S-L Power Modeling Gains Steam
By Ann Mutschler - 12 Jun, 2014 - Comments: 1

Power analysis, architectural exploration and optimization of an SoC is a hot topic of discussion today. It is well accepted this must be addressed at a higher level of abstraction because not just the hardware must be taken into account with power intent and power management structures. It has to be viewed from a system point of view, as well, where the hardware resides along with the opera... » read more

Experts At The Table: The Trouble With Low-Power Verification
By Ed Sperling - 14 Mar, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power verification with Leah Clark, associate technical director at Broadcom; Erich Marschner, product marketing manager at Mentor Graphics; Cary Chin, director of marketing for low-power solutions at Synopsys; and Venki Venkatesh, senior director of engineering at Atrenta. What follows are excerpts of that conversat... » read more

The Double Whammy
By Ed Sperling - 13 Sep, 2012 - Comments: 0

By Ann Steffora Mutschler Given that at 40nm and below every [getkc id="81" kc_name="SoC"] has some mixed-signal content, combined with the fact that power awareness is top priority no matter what the target application is, design teams and verification engineers are grappling with tremendous challenges just to get a chip to yield. “For verification engineers and for designers, this is a ... » read more

Experts At The Table: Improving The Efficiency Of Software
By Ed Sperling - 22 Jun, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Design sat down to talk about how to write better software with Jan Rabaey, Donald O. Pederson Distinguished Professor at the University of California at Berkeley; Barry Pangrle, solutions architect for low-power design and verification at Mentor Graphics; Emily Shriver, research scientist at Intel; Alan Gibbons, principal engineer at Synopsys; and Dav... » read more

Power Modeling: Use Cases Need to be Clearly Defined
By Ann Mutschler - 14 Jun, 2012 - Comments: 0

By Ann Steffora Mutschler Low-Power/High-Performance Engineering sat down to discuss power modeling during the Design Automation Conference with Vic Kulkarni, senior vice president and general manager at Apache Design; Paul Martin, design enablement and alliances manager at ARM; Sylvan Kaiser, CTO at Docea Power; and Frank Schirrmeister, group director, product marketing for system deve... » read more

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