Balancing Parallel Test Productivity With Yield & Cost


Parallel test is used for nearly every device produced by fabs and OSATs, but it can reduce yield and increase the cost of test boards and operations. This is a well-understood tradeoff for ensuring consistent test accuracy across multiple sites and reducing test time. Collectively, ATEs and multi-site test boards — DUT interface boards (DIBs), probe cards, and load boards — significantl... » read more

Cleaning Up During IC Test


Test is a dirty business. It can contaminate a unit or wafer, or the test hardware, which in turn can cause problems in the field. While this has not gone unnoticed, particularly as costs rise due to increasing pin and ball density, and as more chips are bundled together in a package, the cost of dirt continues to be a focus. Cleaning recipes for test interface boards are changing, and analy... » read more