Cleaning Up During IC Test

Dirty probe tips and sockets adversely affect test, which can impact chip reliability.


Test is a dirty business. It can contaminate a unit or wafer, or the test hardware, which in turn can cause problems in the field.

While this has not gone unnoticed, particularly as costs rise due to increasing pin and ball density, and as more chips are bundled together in a package, the cost of dirt continues to be a focus. Cleaning recipes for test interface boards are changing, and analytics are improving to spot problems during test and increase overall equipment efficiency (OEE).

Typically, probe and socket clean-up falls under the banner of maintenance, but it’s a lot more complicated and impactful than it sounds. These operations can affect IC reliability, throughput in a fab or packaging house, and ultimately yield.

Effective manufacturing test requires maintenance of all test cell components, from giant ATE machines to handlers, probers, software, probe cards, and load boards. With repeated probing and socketing, the test boards supporting wafer and package level test become misaligned and contaminated. Dirt increases contact resistance (CRES), which adversely impacts retest rate, yield and equipment up time.

Regular cleaning of probe tips and sockets has been an absolute necessity for test factories. But those cleaning processes affect the lifetime usage of a load board/probe card. As a result, test equipment companies have been searching for an optimal cleaning rate, utilizing analytics to manage cleaning frequency.

The impact of cleaning is often invisible to other engineering teams along the product life-cycle. “What’s least understood about probe and socket test is the frequency and efficacy of cleaning the probe tips and probe materials, such as conductive vs. non-conductive, sticky vs. abrasive, or laser cleaning,” said George Harris, vice president of global test services at Amkor Technology.

The starting point for comprehending the need for cleaning is to understand CRES and its impact to the test process.

CRES basics
In a test environment, one of the key considerations is the ohmic path between a device under test’s signal and power pads/pins to the ATE delivering the necessary voltages and currents. This path has an expected resistance range. The lower the resistance, the better.

Power to the DUT impacts all applied tests. For large, complex SoCs, product engineers are more concerned about the CRES impact to power delivery than signal integrity. For pads/pins dedicated for power delivery, that typically is about 40%. With repeated insertions, dirt accumulates and CRES rises.

Managing contact resistance at wafer test always has been a challenge. It requires just enough force to break a metal oxide without causing product damage.

“For the engineering side, the biggest challenge is understanding how to control the contact resistance of a probe needle — making contact with the die in such a way that you get very low contact resistance, but you don’t damage the pads by essentially overdriving too much or scrubbing too much,” said Mark McLaren, president of Integrated Technology Corp. “The whole issue of pad damage, whether it’s on the surface of the pad or active circuits underneath, is probably the single biggest issue.”

With every touch down to a die, the probe tip gathers a bit more dirt, which increases CRES. And when CRES exceeds the limit, it will impact die test measurement accuracy. With every touch down there also is a bit more damage to the pad/bump, which can impact the assembly process in wirebond and flip-chip packages.

When observing poor CRES, an operator may increase the over-travel a smidge to meet the CRES expectation and perform a retest of the wafer. This increase in over-travel, while making a better electrical contact most likely results in a change of scrub mark characteristics. Similarly, for a testing a packaged die, operators can control the force applied to the pogo pin within the socket to make that inter-metallic contact for a sound electrical transfer.

Fig. 1: CU pillars after probing. Source: FormFactor

“How do you keep the balance of stable contact vs. minimize test pad/bump damage? Current production test requires maximum test efficiency for up to100K contact point, which translates to over 300kg force reaction happening during the test,” said Alan Liao, product marketing director in the probes business unit at FormFactor. “In these high force situations there is a high reaction force back to the probe card. To avoid test pad/bump damage and maintain excellent contact you can use MEMS probe, which greatly reduces probe force. This advanced probe card architecture achieves excellent probe planarity control over a 300mm wafer area. Since 2014, these test challenges have driven the demand for MEMS advanced probe cards.”

For all types of packaging, engineers have been concerned with this balance of force. Wire bond technology still is used for up 75% of packaged parts, and too much overdrive on a pad has negative consequences for later test steps and product quality.

In a 2009 study for wire bond package, entitled “Parameter Modeling for Wafer Probe Test” Fairchild Semiconductor engineers used finite element analysis to comprehend the following parameter’s impact on wafer probe test for die destined for wire bond package: probe over-travel (OT) distance, scrub, contact friction coefficient, probe tip shapes, and diameter. They had a particular concern regarding the impact on the interlayer dielectric layer under the bond pad. Inducing a local tensile stress can cause an ILD failure, which would result in a failure at die level or package level test, which could cause a customer return.

In the test factories the balance game is keeping CRES under a determined limit to maintain the test quality. Over that limit, the yield decreases and retest rate increases, resulting in lower OEE.

Cleaning options
The physics of friction results in wear and tear. In mechanical parts this is reduced by viscous fluids that lessen the metal-to-metal rubbing. Test engineers don’t have that option. And with every insertion within a wafer prober or unit handling system metal-to-metal rubbing occurs. With friction comes debris, wear on a probe tips, pogo-pins and sockets which results in larger CRES values.

“Every time you contact the pad, there is chance of generating particles. The intention with scrubbing pad is to penetrate the aluminum oxide layer to contact the aluminum pad. This process naturally generates AL oxide particles, especially when you test at hot temperature it generates more particles.” said Liao. “When you move to C4 bumps or Cu Pillar solder bump the material melting point is generally lower than aluminum and copper pad. They can melt onto your probe tips which contributes to contact stability property, i.e., CRES.”

Contamination also occurs in the test socket on the load board used for unit-level testing.

“The pins or probes in the socket touch the DUT’s pin or solder ball,” said Dan Campion director and general manager of high-performance contactors at Cohu. “It digs into and breaks through the oxide, and so it will get some of that material on it. Now, a lot of the probes are designed to shed as little of that material as possible. But over time it builds up and you need to use some cleaning approach.”

The industry has responded by adopting cleaning processes at both wafer and unit test. By removing contamination, the CRES of the probe tip or socket interface goes back its starting point.

The actual cleaning technology used varies, depending on the wafer probe technology, contactor technology, and the handling equipment. For sockets, the cleaning approaches vary widely, including brushing the socket, blowing out with compressed air, laser cleaning, and using a cleaning substrate.

“When cleaning the probes of a probe card during wafer sort, the user might implement cleaning materials that are typically an abrasive film,” said Jerry Broz, senior vice president of technology at International Test Solutions. “For less-advanced cantilever or vertical probe cards, when this type of abrasive cleaning is performed, it will remove probe material. This abrasive cleaning will create larger probe tips that will impart bigger scrub marks on the device under test. Since the abrasive cleaning process removes probe material, it also will reduce the probe tip length and impact the usable lifetime of the probe card.”

Fig. 2: Impact of cleaning on cantilever probe tip. Source: SWTest Conference, 2007

With the introduction of MEMS-base probe technologies the industry has developed highly engineered cleaning materials. “The loaded polymer cleaning materials act as debris collectors, but also can provide a polishing action to remove the adherent contamination from the probe tips,” Broz explained. “This type of advanced cleaning is effective for maintaining the contact area texture and preserving the overall shape of the probe tip to maximize the number of touchdowns by probe card.”

Cleaning takes time and has an impact on equipment uptime. With a manual cleaning process, technicians break down the test cell to remove the probe card or loadboard for a manual cleaning process. This has a significant impact on equipment uptime. Today, all probers support in-situ cleaning of probe tips using a cleaning substrate of some sort. In fact, automatic cleaning for wafer probe cards is simply presumed.

Adoption of an automatic cleaning for sockets has been on the rise. Engineers first had to demonstrate that it could be done. “In 2004, we actually introduced this concept of implementing socket cleaning in handlers. At that time the handlers were not configured to accommodate cleaning execution,” said Broz.

The type of package dictates the mechanical interface between the DUT and load-board socket. This, in turn, dictates the cleaning options. Consider the difference between clamping onto a pin for pinned packages as opposed to touching a solder ball with a probe pin in the socket.

The interest in automatic cleaning for sockets corresponds to the growth in ball grid array packaging. Solder balls generate more dirt in a contact than a pin.

“On the solder ball, there are oxides that form, and to make good contact you want to pierce the ball,” said Campion. “In the act of doing that, it inevitably leaves behind residue, whereas if you’re sliding the pin into a receptacle of a socket, there is little to no residue produced.”

In-situ cleaning for package test slight differs from wafer probe test due to the test cell configuration.

“You have a tray of these cleaning devices (CDs), Campion said. “The cleaning material is a DUT surrogate that matches the geometry of the DUT socket interface. You load that tray into the handler. When a cleaning cycle is needed, the CDs are automatically cycled through the handler to the loadboard, just like a device under test. They are inserted into the socket a certain number of times, and then the test cell goes back to production testing.”

Fig. 3: Components for automatic package cleaning. Source: International Test Solutions, a CMC Materials Company

Cleaning frequency
The frequency of cleaning directly affects a test interface’s CRES and the lifetime of the probe tips and socket. While contactor and probe card manufacturers provide guidance on the frequency of cleaning, it always requires customizing to the specific product being tested. Data from testers and test equipment, combined with data analytic platforms, enable engineers and technicians to have a more responsive customization.

With cleaning being essential to both wafer and unit level test success finding the optimal cleaning frequency benefits probe tip, socket life, retest rates, and equipment efficiency. Put simply, it boils down to how often you clean.

“On the tester, after probe card 50 to 100 touchdowns, they will pull in a cleaning wafer to remove any particles attached to probe tip,” said Liao. “However, applying this polishing process also will shave off the probe tip material and shorten a probe’s lifetime. Probe card suppliers and test engineers need to work together to achieve a well-balanced cleaning recipe that is good enough for CRES, and yet not have too much impact on the probe card’s lifetime.”

This requires something of a balancing act. “If factories can squeeze out 0.5% in OEE, that’s actually significant because it adds up over time,” said Keith Schaub, vice president of technology and strategy at Advantest America. “The bigger impact is on test hardware life. You don’t want to clean too often, because every time you go and touch something, that’s wear and tear. If you clean too late, there’s an impact to yield and product quality.”

At final test, the cleaning strategy depends upon the test facility. “The conservative strategy is preventive maintenance,” said Campion. “You automatically clean after so many cycles, e.g. 10,000, or maybe you do it between lots. Another approach is to monitor a specific test parameter — with contact failures over a certain percent you run a cleaning. This is more adaptive, i.e. cleaning done just in time.”

However, he noted that blindly responding to a test parameter can be an issue. So factories also need to monitor the frequency of cleaning, because it can be an indicator of a deeper need like replacing a socket, kit, or checking the alignment of the whole mechanical stack.

Using data analytic platforms, product and test engineers can understand whether the parameters driving retest and triggering cleaning cycles are specific to multi-site test boards.

“To track the die yield and consecutive failures, if the yield for a single test site falls that can trigger a trip to the repair shop,” stated Darren James, technical account manager at Onto Innovation.

With high-volume production — millions of parts per month — there’s been investigations into machine learning algorithms to trigger cleaning cycles.

“When should I clean? They use rules for instance if the contact resistance is too high, or they figure out the number of touchdowns,” said Advantest’s Schaub. “We’re always trying to improve efficiency and operations. You may tend to clean too early, because you don’t want to do it too late. It’s kind of like rotating the tires on your car. You rotate them every 20,000 miles, but it really depends on your driving. If you’re driving straight all the time, then you probably don’t need to do that. You could probably go 30,000 or 40,000 miles. If you’re someone who drives in the city or on curvy roads, and you’re getting a lot of wear, you probably need to do that earlier. That’s kind of the point of machine learning. Machine learning takes that data and figures that out for you, optimizing when should that cleaning happen again.”

Cleaning sockets and probe heads has been there from the start because contact resistance has an adverse impact on testing units and die. Cleaning is essential, but like all steps that interrupt the test process, there ‘s room for improvement.

A preventive maintenance approach often results in cleaning recipes that are too aggressive. Some test facilities have adopted a responsive approach, using test data to dictate the cleaning frequency. It doesn’t matter if the trigger is based upon a statistic bin limit or an algorithm based upon a machine learning. The Goldilocks goal is to achieve just the right amount of cleaning.

The test hardware making that final contact will experience degradation. Concerns about this continue with each advancement in semiconductor process generation and packaging technology. The industry has responded with shifts in cleaning technology and best-known practices to maintain the test hardware essential for that last centimeter of test contact.

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Michael Williams says:

This is a very good discussion of the issues involved in testing products at the wafer level!

Jan Hoppe says:

Very instructive. I know laser cleaning is going.
Many applications including high power so called fiber lasers. Saw big power laser cleaning gear. It cleaned aluminum sheet.

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