tag: Wafer

Challenges Grow For Creating Smaller Bumps For Flip Chips
By Anne Meixner - 18 May, 2023 - Comments: 0

New bump structures are being developed to enable higher interconnect densities in flip-chip packaging, but they are complex, expensive, and increasingly difficult to manufacture. For products with high pin counts, flip-chip [1] packages have long been a popular choice because they utilize the whole die area for interconnect. The technology has been in use since the 1970s, starting with IBM�... » read more

Where And When End-to-End Analytics Works
By Anne Meixner - 10 May, 2022 - Comments: 0

With data exploding across all manufacturing steps, the promise of leveraging it from fab to field is beginning to pay off. Engineers are beginning to connect device data across manufacturing and test steps, making it possible to more easily achieve yield and quality goals at lower cost. The key is knowing which process knob will increase yield, which failures can be detected earlier, and wh... » read more

Big Payback For Combining Different Types Of Fab Data
By Anne Meixner - 07 Dec, 2021 - Comments: 1

Collecting and combining diverse data types from different manufacturing processes can play a significant role in improving semiconductor yield, quality, and reliability, but making that happen requires integrating deep domain expertise from various different process steps and sifting through huge volumes of data scattered across a global supply chain. The semiconductor manufacturing IC data... » read more

Curvilinear Design Benefits For Wafers
By Jan Willis - 21 Oct, 2021 - Comments: 0

Throughout this blog series the focus has been on curvilinear photomasks – the benefits, enablers, and challenges. It leads to the obvious question that Aki Fujimura, CEO of D2S, put to the panel of luminaries. If leading-edge mask shops are ready for curvilinear shapes on mask enabled by curvilinear ILT, multi-beam mask writers and the mask design chain, can we have curvilinear target shapes... » read more

Why Wafer Bumps Are Suddenly So Important
By Anne Meixner - 10 Aug, 2021 - Comments: 2

Wafer bumps need to be uniform in height to facilitate subsequent manufacturing steps, but a push for 100% inspection in packaging in mission-critical markets is putting a strain on existing measurement technologies. Bump co-planarity is essentially a measure of flatness. Specifically, it measures the variation in bump height, which may have a target, for example, of about 100 microns. As a ... » read more

Geo-Spatial Outlier Detection
By Anne Meixner - 19 Jul, 2021 - Comments: 0

Comparing die test results with other die on a wafer helps identify outliers, but combining that data with the exact location of an outlier offers a much deeper understanding of what can go wrong and why. The main idea in outlier detection is to find something in or on a die that is different from all the other dies on a wafer. Doing this in the context of a die’s neighbor has become easie... » read more

Cleaning Up During IC Test
By Anne Meixner - 06 Jul, 2021 - Comments: 2

Test is a dirty business. It can contaminate a unit or wafer, or the test hardware, which in turn can cause problems in the field. While this has not gone unnoticed, particularly as costs rise due to increasing pin and ball density, and as more chips are bundled together in a package, the cost of dirt continues to be a focus. Cleaning recipes for test interface boards are changing, and analy... » read more

Using Fab Sensors To Reduce Auto Defects
By Anne Meixner - 09 Jun, 2020 - Comments: 0

The semiconductor manufacturing ecosystem has begun collaborating on ways to effectively use wafer data to meet the stringent quality and reliability requirements for automotive ICs. Silicon manufacturing companies are now leveraging equipment and inspection monitors to proactively identify impactful defects prior to electrical test. Using machine learning techniques, they combine the monitor ... » read more

Controlling Uniformity At The Edge
By Aaron Eppler - 19 Oct, 2017 - Comments: 0

Chipmakers want every part of the wafer to produce, or yield, good die. Advances in process technologies over the years have just about made this a reality, even as feature dimensions continue to shrink and devices grow ever more complex. Now, the last frontier is improving yields at the edge of the wafer – the outer 10 mm or so – where chemical, physical, and even thermal discontinuitie... » read more

Applied To Buy TEL
By Mark LaPedus - 24 Sep, 2013 - Comments: 0

In a deal that could shake-up the fab tool landscape, Applied Materials has announced a definitive agreement to acquire rival Tokyo Electron Ltd. (TEL) in a stock deal valued at around $9.3 billion. Under the terms of the blockbuster deal, Applied Materials will own approximately 68% of the new company and TEL will own about 32%.  The combined entities will have a new name, dual headquarter... » read more

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2023 SMG   |  Terms of Service  |  Privacy Policy