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Why Wafer Bumps Are Suddenly So Important

As density increases, so does the risk of chip failures.

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Wafer bumps need to be uniform in height to facilitate subsequent manufacturing steps, but a push for 100% inspection in packaging in mission-critical markets is putting a strain on existing measurement technologies.

Bump co-planarity is essentially a measure of flatness. Specifically, it measures the variation in bump height, which may have a target, for example, of about 100 microns. As a statistical process control limit, engineers may flag deviations greater than 3%, which in this case would be ± 3µm. The height unevenness in a bump array affects wafer probing, flip-chip assembly, and electronics board assembly — and ultimately, reliability.

Uneveness becomes particularly important in the context of the increasing bump densities in high-performance computing products and other advanced packaging applications, which require more stringent inspection and metrology steps. But to achieve this co-planarity, higher throughput and measurement resolution are necessary.

It also requires different measurement equipment to work in sync. The risk of a bad die connection needs to be managed during both process development and manufacturing. At each of those stages, both metrology and inspection systems are required to achieve consistent manufacturing of bumps and pillars. The former is measured at the micron or nanometer level, while the latter’s measurements are in the range from tens to hundreds of microns. Inspection and metrology companies are improving their solutions with these demands in mind.

Applying well-known optical interferometry techniques and the associated computer vision mathematics, these companies can provide the measurements needed to assess bump height, size, and position. These improvements have evolved from companies with competencies in surface-mount technology (SMT), package assembly — which have developed measurement techniques for flatness, and wafer processing — which has long addressed the sub-micron metrology.

“Our optical measurements use white light interferometry technology, which is a limitation on the X and Y resolution — that’s the lateral resolution. The reason why an engineer or scientist would use our technology is because they’re more interested in the Z resolution,” said Robert Cid, product manager for nano surfaces at Bruker. “The Z resolution is becoming more important, especially for advanced packaging, because they want to know what the planarization, Z-variation, of the die is before they start assembling them into an advanced package. Currently, for Z resolution, we’re getting repeatability down to about 0.15 nanometers.”

Others are moving into measuring bump Z variation, as well. “My group works on the computer vision for our 3D sensors, and we focus on three application areas — circuit board inspection, semiconductor package inspection, and mid-end inspection,” said John Hoffman, computer vision engineering manager at CyberOptics. “Mid-end inspection, which is measuring bumps on wafers, is a new market for us. We sell our sensors to KLA, which they use for their back-end semiconductor packaging inspections. And we’re moving that experience closer to the back end. We’re calling it the mid-end, measuring wafer bumps with 20 micron features up to 200 micron features.”

Wafer bump inspection and metrology assist in both process development and production environments. Their primary goal is to improve the overall yield associated with bump characteristics. However, as of today, this relationship is not well understood.

“Today in backend/package inspection, we don’t have well-established correlations between inspection and the assembly process,” said Olivier Dupont, product marketing manager in KLA’s ICOS Division. “This is an area for future development that needs to be built. And as many observe, advanced packaging growth continues to progress. It has to invest in this kind of development.”

Bump co-planarity impact
A consistent bump height, or co-planarity, is critical to the assembly process. Unevenness in bump position and height will impact the creation of a sound intermetallic bond at assembly, or a low-contact-resistance contact at wafer test.

Conceptually, both processes simply match two metal arrays to pass electricity. One takes an array of bumps on a wafer and matches them to an array of probe tips. The other takes an array of bumps on a die and matches them to an array of pads/bumps on a substrate assembly.

To create that electrical connection, each requires mechanical positioning to align arrays within the X,Y direction and to close the gap in the Z direction. Across an array of bumps, variation in height directly affects Z direction position and ultimately the quality of that electrical connection.

Consider overtravel requirements for wafer probing, for example. “The test equipment will determine which pad makes first contact to your probe card, and which pad makes last contact,” said Alan Liao, product marketing director in probes business unit at FormFactor. “This is your probe card planarity. Now, with the electrical planarity setting after the last contact, you over-travel another 30 or 40 microns to make sure you have a stable contact.”

The overtravel in the Z direction guarantees that contact. With Al pads there exists little to no concern regarding their unevenness in the Z direction. Move to C4 bumps and Cu pillars (a.k.a. C2), and height variation impacts the wafer probing process. With a 200-micron bump height, 10% variation in height directly impacts the overtravel needed during wafer probe. Decrease to 50-micron bump height, and that same 10% variation has a greater impact. It becomes a delicate balance between achieving the temporary intermetallic contact and adversely effecting the subsequent assembly process.

Moving on to the assembly process, engineers rank bump height variation as the attribute of the utmost interest.

“Our customers are most interested in bump height, bump diameter, and positioning of the bump relative to their CAD model,” said Hoffman. “Characterizing the shape of these bumps is not interesting to them. Their process is dialed in enough so that that’s very consistent. What isn’t consistent, typically, is the variability in the heights. Coplanarity is their biggest concern, which makes sense. If they’re perfectly coplanar, you just smack them together and you’re done. But if they’re not co-planar, by how much? How much do they account for that in the reflow process? How much will these balls expand during the reflow process?”

Cyberoptics

Fig. 1: Parameters that must be controlled for bumping processes include height, coplanarity, position, size, and shape. Source: CyberOptics

Much of the ball grid array packaging uses the reflow process, which enables the bumps to self-align. A shift to thermal compression bonding has begun, which also heightens interest in planarity.

“You’re actually placing the die, then applying heat and force at the same time to form the bond,” said Scott Jewler, COO of SXVR. “You no longer get the benefit of surface tension self-aligning the die because you are holding the die in a constant position. This results in more process variables — planarity of the die to the substrate, tilt, and X,Y alignment.”

Comprehending the process variables in bump formation that impacts co-planarity requires measurement data in the Z-direction.

Z-direction images
Optical wavelength-based measurement systems remain the primary methodology used by equipment suppliers. The capability to acquire images is impacted by an imaging instrument’s field of view, wavelength(s) of light, and the signal processing algorithms. For the latter, suppliers use computer vision-specific algorithms, which electronics and semiconductor manufacturers have used for decades.

Bump manufacturing engineers, meanwhile, use metrology equipment for process development experiments and periodic process control checks. While they can use inspection equipment for process control, they primarily use it for finding anomalies, such as defects. Inspection typically has been done on a sampling basis, which can be a percentage of wafers, a percentage of bumps on all wafers, or a percentage of bumps on the percentage of wafers. Still, the need for 100% inspection of wafer bumps and package bumps increases every year, and a major reason is improved and real-time process control.

A key differentiating characteristic between metrology and inspection equipment is the speed of image acquisition and interpretation. With metrology systems, the measurement needs to be accurate and at the required resolution for engineers to make their assessments. For example, engineers use the measurements as feedback in developing or revising a bump recipe, or in qualifying new equipment. Time for measurement acquisition is not crucial.

In contrast, manufacturers embed inspection systems in production. The measurements need to be accurate enough for an automated system to make a quick go/no-go decision on the wafer or package. For inspection purposes, supervised machine learning tunes a computer vision algorithm to meet the accuracy and decision time requirements. Tuning could require from 10 to 50 good images to set the pass/fail/disposition thresholds.

All optical wave-length based measurements work on the principle of projecting light to a sample’s surface, detecting the light that bounces and then computing on the detected light to discern an attribute of interest.

“In a laser-based system you do localized surface heating and then observe the reflected signal back with some type of detector, said Ben Miehack, product manager for defect inspection and metrology at Onto Innovation. “It’s extremely slow and not really suitable for high-volume manufacturing, unless you had some means to indicate a failure occurred in a region and then you targeted that region. In terms of wafer bumping, looking at the composition of the bumps or pillars one can use a high-speed technique to look for outliers, and then use something with much higher resolution to pinpoint its characteristics.”

Interferometry-based techniques can be used to view a wider sample area. Profilometer instruments specifically measure X,Y,Z dimensions of the sample’s surface. “White-light interferometry works on the same principles as interferometry, where you’ll have a reference beam that goes off into one direction and then light bouncing off your sample,” said Bruker’s Cid. “When they combine at the imaging array, you end up with a 3D representation of the surface.”

Both process development and manufacturing applications rely on repeatable and reproducible measurements. Equipment suppliers alike strive for this. And as stated earlier, measurement speed determines metrology vs. inspection usage. When it comes to choosing between 100% or sampled inspection, an engineering manager considers the bump process maturity and cost.

“If your manufacturing process is mature, i.e., very low variability, you can probably get by sampling 1% of your wafers — maybe only 1% of the bumps on 1% of your wafers,” said CyperOptics’ Hoffman. “But if you’re pushing the process technologies such that you have 5% failures, you can’t do sampling inspection in that kind of environment. With every market that we operate in, we always have operated in 100% inspection. As we bring this capability to the market, it’s interesting to see the market come to terms with this capability.”

From image to interpretation
The path from image to interpretable data to actions relies upon algorithms, domain knowledge, and statistics.

Interpreting the reflected light back from a surface requires a deep understanding of physics for both the measurement system and surface attributes. Signal processing algorithms form the basis of the computer vision used to make measurements in the Z direction.

In terms of surface area specific to bump measurements, it can be a whole wafer or a single diced device or a package substrate. Feature size, not sample size, dictates the signal processing algorithms used, and there’s usually more than one algorithm being used.

“What can change the algorithms is the way that our sensor observes a 25-micron bump, which is fairly different from how it observes a 100-micron bump,” Hoffman said. “But that typically doesn’t manifest itself in the algorithms that we write. It typically manifests itself in the algorithms that our customers write. The interface from the sensor to the OEM is a height map. The OEM’s responsibility is to take that height map and extract the interesting information. We collaborate extensively with the OEMs on this extraction. We come up with algorithms that we recommend to them.”

Connecting the bump characteristics to the yield of the assembled package motivates looking at the overall bump characteristics.

“On the packaging side, customers want to know how homogeneous the bumps are — not only the diameter of the bumps, but also the overall height of the bumps and the roughness on top of the bumps,” said Bruker’s Cid. “Once a bumped wafer goes into the final assembly, they can understand how these structural attributes impact final test yield.”

As with electrical test, engineers who care about bump characteristics have started to look beyond statistical process control limits for outliers.

“These outliers are within the noise, because you can have a measurement or process which meets the control limits, but it’s actually deviating in some way,” said Onto’s Miehack. “So, it passes all the control limits, but it’s varying. For instance, they all pass their height control limit within 2% to 6% of the process control target. ‘However, this part of the wafer has 4%, whereas the rest of it is 2%.'”

Engineers could find value in that interpretation of the data, and a 100% inspection of bump height provides more data for interpretation. The possible actions that engineers can take with this granularity of data include:

  • Revising the bump manufacturing recipe;
  • Correlating wafers with outliers to equipment and associated maintenance records;
  • Adjusting to die-level bump height variability at the next assembly manufacturing step.

Summary
Measuring wafer bump characteristics has grown in importance. Engineers require improvements in both inspection and metrology of bumps.

In all industry sectors end customers have raised their quality and reliability expectations. This drives 100% inspection needs. Inspection of every bump provides enhanced understanding of bump characteristics’ relationship to yield, which in turn opens up new opportunities for process optimization or cost reduction. Naturally, packaging density requirements continue to push bump process technologies and the high-resolution images from metrology systems increase comprehension of subtle changes inherent in manufacturing at tens of microns.

Five years ago, packaging facilities had concerns regarding trending measurements needs and the capability of existing inspection equipment. “Today, that’s no longer the case. We have gotten technologies to do that better. Camera technologies have gotten better, light sources have gotten better,” said Onto Innovation’s Miehack. “It will get there. It’s just taking time. It’s more about who will get there first in a cost-effective manner.”

— Susan Rambo contributed to this story.

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2 comments

David Leary says:

Is CMP polishing, or alternatively coining (compression) not a solution to assuring bump co-planarity, instead of the complexity of inspection?

Anne Meixner says:

David,

I suspect that CMP is not an option as my understanding is that CMP polishes to a flat surface. Wafer bumps, be they C4, C2 (aka pillars) by their very nature are an uneven surface.

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