Digging Much Deeper With Unit Retest

It’s no longer just an automatic retest to improve yield. Rising product complexity, pressures on manufacturing costs, and better data are making this process more nuanced.


Keeping test costs flat in the face of product complexity continues to challenge both product and test engineers. Increased data collection at package-level test and the ability to respond to it in a never-before level of detail has prompted device makers and assembly and test houses to tighten up their retest processes.

Test metrology, socket contamination, and mechanical alignment have always been the basis for package retest, and when parts don’t pass those tests automatically retest occurs at least once. But unlike in the past, data analytic platforms now enable test and product engineers to look more deeply at the whole retest process. In addition, smart manufacturing investments in assembly and test houses have increased their ability to more rapidly respond to data generated from both test cell equipment and device data. All of this is making the retest process more informative and stringent.

Assembly and test factories typically have reader boards to show all employees the number of units shipped, reinforcing an expectation for high yields after a die is assembled into a package. A yield of 99.5% is not uncommon for a high-volume consumer electronics product, and for decades retesting has been considered a way to nudge that yield upward by recovering good parts marked as failed and to generate more parts in a bin split for a specific parameter such as low power.

Frequently, an expectation of yield recovery is warranted due to such factors as contact resistance. Unit-level testing requires the same high-quality intermetallic contact as a wafer probe. The same metallurgical and mechanical attributes for inserting a device under test (DUT) into a contactor that interfaces with an ATE exist for final test, as well. Those attributes contribute to contact resistance, which in turn affects test results.

For package retest, in particular, performance-based tests often can be done only at the unit level. If the device specifications are at the edge of the ATE’s measurement capability, retest may recover a part that is technically good.

“On package test, it’s very common to retest all sorts of parameters, and it’s almost like test until pass,” said Keith Schaub, vice president of technology and strategy at Advantest America. “At first glance this seems illogical. It failed, so it should remain a failed part. But there are a lot of cases where you are testing at the very limit of the tester. In these cases, retest of a failed unit will become a good unit, and it’s valid.”

So how many retests are enough to ensure valid good parts? “There can be a lot of retest of packaged units,” said Stéphane Iung, senior manager applications silicon lifecycle analytics at Synopsys. “The retest rate is relatively high at final test compared to a wafer. It is something that our customers are very concerned about in terms of cost and quality.”

But with improved data analytic solutions for semiconductor manufacturing test engineering teams can become more nuanced in their understanding of the impact of retest.

The why and ways of retest
Wafer test filters out a high percentage of fab-induced manufacturing defects and process variability. At final test, engineers focus their screens for packaging-related defects and performance binning. For high-volume products, that often includes temperature-sensitive defects.

“At final test, the fundamental assumption is that a large fraction of the first-pass yield loss will be test process-related, so then it can be recovered,” said Iung. “So systematically, final test fails, they go into retest. If the first retest fails, they go into secondary test. Then, with respect to how many retests, it depends on the policy of the individual company.”

Retest of a packaged device can occur in a variety of scenarios, including:

  • As part of the test measurement process;
  • During the test program;
  • In-situ with the first physical handling of the unit lot size, moving failed or down-binned parts to a different test cell, and
  • During quality assurance testing that is required on a sample of good parts.

Fig. 1: Retest possibilities. Source: Semiconductor Engineering/Anne Meixner

Fig. 1: Retest possibilities. Source: Semiconductor Engineering/Anne Meixner

For most devices this retest process depends upon both the design margin to a test pass/fail limit, the ATE’s instrument measurement capability and the test cell equipment reliably creating a good quality contact.

The increasing number of parametric measurements made for devices that support 4G/5G and safety critical applications like automotive and medical can also be at the edge of a pass/fail limit set. Both ATE capabilities and design margin play a roll in being at the edge.

“On most analog devices it’s very common to perform retest of parametric measurement, and this is especially true for the lower signal levels, i.e., 10 millivolts,” said Advantest’s Schaub. “The lower the signal level, the more retest is done as part of the measurement process. You need to do a lot of averaging of test measurements for these very low signal levels. Suppose this takes 10 seconds. Nobody will pay for that amount of test time. So most of the time, good parts pass on the first test. Suppose 10% of the good parts are not going to pass. When acceptable, we test a second time, and these good parts pass.”

Similar to the ATE instrumentation being pushed to its metrology limits, a device may be close to a pass/fail limit.

“Suppose a product has parametric distributions with tight limits. What you see in marginal parts is they fail the first time, and then you retest the part it passes and you have recovered it,” said Synopsys’ Iung. “Yet a lack of reproducibility of the measurement reflects that its recovery is by chance. With retest once and recover, this may be not such a big problem. But if you start to retest many times, in effect you are widening your limits.”

Most recovered units occur with new insertion of a unit into the load board or into a different test cell. Such recovery points to the electro-mechanical nature of test and how the issues can often be remediated by the re-socketing.

Contamination, variation, and stress
Test equipment applies the mechanical forces that assures an intermetallic contact between the DUT and the ATE. Similar to wafer probe test process, a physical alignment is needed to properly situate the unit into a socket on a load board. To make the physical connection to the ATE, a spring-activated pin completes the electrical connection between the DUT and the ATE.

Contact resistance, or Cres, provides a metric to assess the quality of the contact.

“Fundamentally, the same physics of contamination occurs at both wafer and final test, and this either increases Cres or creates a full open,” said Ira Feldman, principal consultant at Feldman Engineering and general chair of TestConX. “This creates variability in the contact, and mechanically an increase in force will remove the variability. Typically, one would increase the force because most contacts have a force versus displacement curve. The further you displace it, the force rises predominately in an exponential manner.”

Just as too much force can damage circuitry under a die pad/ball, the same holds true for package test.

“What’s least understood about the role and impact for unit socket is the interaction between physical stress on the active circuits during test relative to the final application assembly environment and its impact on long-term reliability,” said George Harris, vice president of global test services at Amkor Technology.

With a significant increase in Cres, engineers first look to contamination in the socket. By retesting after reinserting the unit, the part is recovered. But an increase in force to reduce Cres also can be due to mechanical alignment.

“The interaction between the different elements of the mechanical system stack can translate to an over-constrained system if not approached holistically,” said Dan Campion, director and general manager of high-performance contactors at Cohu. “You must consider the relationship between the handler, change kit on the handler, and how that interfaces with the socket, package variations for the DUT in the socket, and the probe element, which makes the contact between the DUT and tester PCB pads.”

Contamination of the physical contact between the DUT and socket is the most likely culprit, which in turn requires cleaning of the sockets if there is a high level of retest. Repeated insertions of units into the socket generates debris and wears down the metal surfaces of the contact mechanism. The resulting increase in contact resistance then boosts the retest rate, and at a certain threshold test operations require a cleaning step for the load board/socket.

The nature of the package, contactor, and handler equipment dictate the cleaning process. Monitoring a number of parameters can show the frequency of cleaning required to manage both overall equipment efficiency (OEE) and expected yield values. This can be detected by monitoring key test measurements that indicate higher than desired contact resistance, as well as statistical bin limits. There are also numerous test process parameters that test factories can monitor.

“Test processes that need to be monitored include temperature control, external forces on the package, electrical and thermal contact performance over time, material handling accuracy — motion accuracy X, Y, Z, and rotation — as well as electrical contact resistance, site-to-site variations, physical dimension of the probing material (length/width and size min/max), planarity, alignment, spring characteristics over time, and re-socket count for ball or pad impacts,” said Amkor’s Harris.

Analytics and retest
Whether determining the source of variability in a fleet of test cells, or the poor yield recovery in a mature product, engineers and technicians use available data to figure out how this is happening. Data from yield management systems and manufacturing execution systems are the first platforms to be used. These same platforms also can be used to improve overall test efficiency and manage costs.

Harris noted that a data analytics platform can provide his engineering staff the ability to examine yield recovery and retest. They can consider the following questions:

  • What is the impact of the product health indicators, such as re-test success rates vs. cost or product test stress limits?
  • What is the danger of performance binning under different use conditions?
  • What is the cost impact?
  • What is the danger of retest if the first-pass “fail” was real, then “healing” occurred during that first-pass impact and then with a re-test “pass,” and later a quality reliability failure occurs in the field from defect re-growth?

It’s easy to get quite nuanced with the kinds of final test process issues that can be investigated. “Product engineers need to check for site-to-site variance. They also need to be able to look for ‘never happen’ events like piggy-backing (stuck device/unit in handler),” said Greg Prewitt, director of Exensio solutions at PDF Solutions. “In addition, they need to look for contactor induced failures — testing that damages the device and would require retest.”

This refinement in the retest process includes asking if all tests should be retested.

“If you analyze the recovery rates of hard bins, or even soft bins, you can determine the ROI of retesting,” said Iung. “Suppose a certain fail bin doesn’t recover well — let’s say only in 5% of the cases. Then the test cost isn’t even worth it to recover the part. It is more expensive to retest than the gain that you will get. You can even have negative ROI, for example, if the recovery rate was 1%.”

Advantest’s Schaub highlighted another side of using data to analyze retest options. “One of the things you can do with all of this data is you can get a prediction on the retest. So instead of just retesting to recover, you can send some previous product data plus the live data over to the model. And the model gives you back a prediction on whether you should retest or not. This is just an operational improvement, which can save a lot of test time and hence cost. For devices that don’t need it, just don’t do it. What generally happens is you fix the number of retests — for example three — and if on the third test the device doesn’t pass, it is marked a fail. But maybe the prediction states this is a good device and it will pass in a customer system. So now you’re throwing away a good device.”

The actual break-even point for retest per test type would depend upon device price, device manufacturing cost (including all test costs), the added cost of retest, and test fallout to a particular test bin and the recovery rate.

Today, retesting a packaged unit at least once is often automatic. This decades old practice has been motivated by the realities of the electromechanical environment of unit insertion, and pushing ATE instrumentation to its specification limits. Yet with ongoing concerns on operation efficiencies, the cost of retest and customer quality engineers and their management are starting to ask whether that retest actually should be automatic.

“Retest is a necessary part of the test operations process, but the ultimate value of retest is how it impacts yield and quality,” said PDF Solutions’ Prewitt. “Maximizing the value of retest is contingent on the ability to create and apply intelligent retest rules during wafer probe and final test. Using these rules to quickly and accurately identify deterministic operational issues and take immediate action is what enables semiconductor companies to efficiently reduce escapes and provide higher quality parts to their end customers.”

With better data from equipment and product coupled with an analytics platform that comprehends semiconductor test, engineering teams can create a more equal yield/cost/quality triangle.

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