tag: contact resistance

Overview of ALD-Driven Oxide Semiconductors for High Density, Low Power Memory Architectures (Hanyang Univ., imec)
By Technical Paper Link - 25 Jan, 2026 - Comments: 0

A new technical paper titled "Oxide Semiconductor for Advanced Memory Architectures: Atomic Layer Deposition, Key Requirement and Challenges" was published by researchers a Hanyang University and imec. Abstract "Oxide semiconductors (OSs), introduced by the Hosono group in the early 2000s, have evolved from display backplane materials to promising candidates for advanced memory and logic ... » read more

Better Contact Resistance in Top-Gate CNFETs through Self-Aligned MoOx Nanoparticle Contact Doping (NYCU et al.)
By Technical Paper Link - 24 Jan, 2026 - Comments: 0

A new technical paper titled "Improving Contact Resistance in Top-Gate Carbon Nanotube Transistor through Self-Aligned MoOx Nanoparticle Contact Doping" was published by researchers at National Yang Ming Chiao Tung University and National Center for Instrumentation Research. "Carbon nanotubes (CNTs) are promising candidates for next-generation back-end-of-line (BEOL) compatible devices due t... » read more

Wafer Probe Struggles To Adapt To Multi-Die Assemblies
By Gregory Haley - 13 Jan, 2026 - Comments: 1

Wafer probe, one of the key processes for ensuring reliability in semiconductor manufacturing, is becoming increasingly unreliable in multi-die assemblies and at leading-edge nodes. For much of the semiconductor industry’s history, wafer probe occupied a stable, largely uncontested role in manufacturing. It was understood as a screening step, an electrical checkpoint to identify failing de... » read more

The Hidden Cost Of Contact Resistance
By Gregory Haley - 09 Sep, 2025 - Comments: 1

Contact resistance, or CRES, is one of those problems that most engineers prefer not to think about until it's staring them in the face. For years, it could be managed quietly with routine probe card cleaning or a scheduled socket swap. That approach worked well enough when pin counts were lower and devices pulled less current, but the ground has shifted since then. Today’s AI processors m... » read more

Simulation Study Of Vertically Stacked 2D NSFETs
By Technical Paper Link - 12 Feb, 2025 - Comments: 0

A new technical paper titled "Simulation of Vertically Stacked 2-D Nanosheet FETs" was published by researchers at Università di Pisa and TU Wien. Abstract "We present a simulation study of vertically stacked 2-D nanosheet field-effect transistors (NSFETs). The aim of this investigation is to assess the performance and potential of FinFET alternatives, i.e., gate-all-around (GAA) nanosheet... » read more

Early Detection Of C-RES Degradation On High-Current Power Planes
By Brent Bullock - 11 Feb, 2025 - Comments: 0

Probe-card or device contactor damage can be dramatic and catastrophic, with yield dropping drastically very quickly. What is not dramatic is the hypothesized slow probe needle or contactor degradation process that might precede catastrophic failure. Such degradation is difficult to detect in the early stages, when probe cards, die, and packages continue to yield normally. A key goal is to dete... » read more

Balancing Parallel Test Productivity With Yield & Cost
By Anne Meixner - 12 Nov, 2024 - Comments: 0

Parallel test is used for nearly every device produced by fabs and OSATs, but it can reduce yield and increase the cost of test boards and operations. This is a well-understood tradeoff for ensuring consistent test accuracy across multiple sites and reducing test time. Collectively, ATEs and multi-site test boards — DUT interface boards (DIBs), probe cards, and load boards — significantl... » read more

Potential Of 2D Semi-Metallic PtSe2 As Source/Drain Contacts For 2D Material FETs
By Technical Paper Link - 13 Aug, 2024 - Comments: 0

A technical paper titled “Improvement of Contact Resistance and 3D Integration of 2D Material Field-Effect Transistors Using Semi-Metallic PtSe2 Contacts” was published by researchers at Yonsei University, Korea Advanced Institute of Science and Technology (KAIST), Lincoln University College, Korea Institute of Science and Technology (KIST), and Ewha Womans University. Abstract: "In this ... » read more

GaN Devices: Properties and Performance At Extremely High Temperatures
By Technical Paper Link - 28 May, 2024 - Comments: 0

A new technical paper titled "High temperature stability of regrown and alloyed Ohmic contacts to AlGaN/GaN heterostructure up to 500 °C" was published by researchers at MIT, Technology Innovation Institute, Ohio State University, Rice University and Bangladesh University of Engineering and Technology. Abstract "This Letter reports the stability of regrown and alloyed Ohmic contacts to A... » read more

Using Palladium To Address Contact Issues Of Buried Oxide Thin Film Transistors
By Technical Paper Link - 09 Apr, 2024 - Comments: 0

A new technical paper titled "Approach to Low Contact Resistance Formation on Buried Interface in Oxide Thin-Film Transistors: Utilization of Palladium-Mediated Hydrogen Pathway" was published by researchers at Tokyo Institute of Technology and National Institute for Materials Science (NIMS). Abstract "Amorphous oxide semiconductors (AOSs) with low off-currents and processing temperatures... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy