tag: contact resistance

Using Palladium To Address Contact Issues Of Buried Oxide Thin Film Transistors
By Technical Paper Link - 09 Apr, 2024 - Comments: 0

A new technical paper titled "Approach to Low Contact Resistance Formation on Buried Interface in Oxide Thin-Film Transistors: Utilization of Palladium-Mediated Hydrogen Pathway" was published by researchers at Tokyo Institute of Technology and National Institute for Materials Science (NIMS). Abstract "Amorphous oxide semiconductors (AOSs) with low off-currents and processing temperatures... » read more

Estimating the Embedded Gate Resistance to Reproduce SiC MOSFET Circuit Performance (ROHM)
By Technical Paper Link - 06 Oct, 2023 - Comments: 0

A technical paper titled “Improved Scheme for Estimating the Embedded Gate Resistance to Reproduce SiC MOSFET Circuit Performance” was published by researchers at ROHM Company. Abstract: "The intrinsic gate resistance ( Rg_in) , which is a novel resistance factor embedded in transistors, was determined for silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFE... » read more

Reducing Contact Resistance in Developing Transistors Based On 2D Materials
By Technical Paper Link - 10 Mar, 2023 - Comments: 0

A new technical paper titled "WS2 Transistors with Sulfur Atoms Being Replaced at the Interface: First-Principles Quantum-Transport Study" was published by researchers at National Yang Ming Chiao Tung University. Abstract "Reducing the contact resistance is one of the major challenges in developing transistors based on two-dimensional materials. In this study, we perform first-principles ... » read more

Modeling and Thermal Analysis of 3DIC
By Technical Paper Link - 13 Feb, 2023 - Comments: 0

A new technical paper titled "Heat transfer in a multi-layered semiconductor device with spatially-varying thermal contact resistance between layers" was published by researchers at UT Arlington. "This work presents a theoretical model to determine the steady state temperature distribution in a general M-layer structure with spatial variation in thermal contact resistance between adjacent la... » read more

Functional-Engineered MXene Transistors
By Technical Paper Link - 28 Sep, 2022 - Comments: 0

A new technical paper titled "High-throughput design of functional-engineered MXene transistors with low-resistive contacts" was published by researchers at Indian Institute of Science (IISc) Bangalore. Abstract (partial): "Two-dimensional material-based transistors are being extensively investigated for CMOS (complementary metal oxide semiconductor) technology extension; nevertheless, down... » read more

Reporting and Benchmarking Process For A 2D Semiconductor FET
By Technical Paper Link - 29 Jul, 2022 - Comments: 0

New research paper titled "How to Report and Benchmark Emerging Field-Effect Transistors" was published from researchers at NIST, Purdue University, UCLA, Theiss Research, Peking University, NYU, Imec, RWTH Aachen, and others. "Emerging low-dimensional nanomaterials have been studied for decades in device applications as field-effect transistors (FETs). However, properly reporting and compar... » read more

Pinpointing the Dominant Component of Contact Resistance to Atomically Thin Semiconductors
By Technical Paper Link - 08 Mar, 2022 - Comments: 0

Abstract "Achieving good electrical contacts is one of the major challenges in realizing devices based on atomically thin two-dimensional (2D) semiconductors. Several studies have examined this hurdle, but a universal understanding of the contact resistance and an underlying approach to its reduction are currently lacking. In this work we expose the shortcomings of the classical contact resist... » read more

Digging Much Deeper With Unit Retest
By Anne Meixner - 08 Jun, 2021 - Comments: 0

Keeping test costs flat in the face of product complexity continues to challenge both product and test engineers. Increased data collection at package-level test and the ability to respond to it in a never-before level of detail has prompted device makers and assembly and test houses to tighten up their retest processes. Test metrology, socket contamination, and mechanical alignment have alw... » read more

Managing Wafer Retest
By Anne Meixner - 19 May, 2021 - Comments: 1

Every wafer test touch-down requires a balance between a good electrical contact and preventing damage to the wafer and probe card. Done wrong, it can ruin a wafer and the customized probe card and result in poor yield, as well as failures in the field. Achieving this balance requires good wafer probing process procedures as well as monitoring of the resulting process parameters, much of it ... » read more

Inside Next-Gen Transistors
By Mark LaPedus - 20 Apr, 2017 - Comments: 0

David Fried, chief technology officer at [getentity id="22210" e_name="Coventor"], sat down with Semiconductor Engineering to discuss the IC industry, China, scaling, transistors and process technology. What follows are excerpts of that conversation. SE: In a recent roundtable discussion you talked about some of the big challenges facing the IC industry. One of your big concerns involves th... » read more

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