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Reliability Costs Becoming Harder To Track


Ensuring reliability in chips is becoming more complex and significantly more expensive, shifting left into the design cycle and right into the field. But those costs also are becoming more difficult to define and track, varying greatly from one design to the next based upon process node, package technology, market segment, and which fab or OSAT is used. As the number of options increases fo... » read more

Digging Much Deeper With Unit Retest


Keeping test costs flat in the face of product complexity continues to challenge both product and test engineers. Increased data collection at package-level test and the ability to respond to it in a never-before level of detail has prompted device makers and assembly and test houses to tighten up their retest processes. Test metrology, socket contamination, and mechanical alignment have alw... » read more

Managing Wafer Retest


Every wafer test touch-down requires a balance between a good electrical contact and preventing damage to the wafer and probe card. Done wrong, it can ruin a wafer and the customized probe card and result in poor yield, as well as failures in the field. Achieving this balance requires good wafer probing process procedures as well as monitoring of the resulting process parameters, much of it ... » read more

Chip Monitoring And Test Collaborate


As on-chip monitoring becomes more prevalent in complex advanced-node ICs, it’s easy to question whether or not it conflicts with conventional silicon testing. It might even supplant such testing in the future. Or alternatively, they could interact, with each supporting the other. “On-chip monitors provide fine-grained observability into effects and issues that are otherwise difficult or... » read more

Testing Analog Circuits Becoming More Difficult


Foundries and packaging houses are wrestling how to control heat in the testing phase, particularly as devices continue to shrink and as thermally sensitive analog circuits are added into SoCs and advanced packages to support everything from RF to AI. The overriding problem is that heat can damage chips or devices under test. That's certainly true for digital chips developed at advanced node... » read more

Chasing Test Escapes In IC Manufacturing


The number of bad chips that slip through testing and end up in the field can be significantly reduced before those devices ever leave the fab, but the cost of developing the necessary tests and analyzing the data has sharply limited adoption. Determining an acceptable test escape metric for an IC is essential to improving the yield-to-quality ratio in chip manufacturing, but what exactly is... » read more

A Novel Memory Test System With An Electromagnet For STT-MRAM Testing


We have successfully developed, for the first time, a new memory test system for STT-MRAM at wafer-level where an electromagnet is combined with a memory test system and a 300 mm wafer prober. In the developed memory test system, an out-of-plane magnetic field up to ±800 mT can be applied on 10 x 10 mm2 in the 300 mm wafer with distribution of less than 2.5%. We demonstrated that the electroma... » read more

AI In Inspection, Metrology, And Test


AI/ML is creeping into multiple processes within the fab and packaging houses, although not necessarily for the purpose it was originally intended. The chip industry is just beginning to learn where AI makes sense and where it doesn't. In general, AI works best as a tool in the hands of someone with deep domain expertise. AI can do certain things well, particularly when it comes to pattern m... » read more

Sharing Secure Chip Data For Analytics


New approaches and standards are being developed to securely share manufacturing and test data across the supply chain, moves that have long been considered critical to the reliability of end devices and faster time to yield and profitability. It will take time before these methods become widespread in the IC supply chain. But there is increasing agreement these kinds of measures are essenti... » read more

What Goes Wrong In Advanced Packages


Advanced packaging may be the best way forward for massive improvements in performance, lower power, and different form factors, but it adds a whole new set of issues that were much better understood when Moore's Law and the ITRS roadmap created a semi-standardized path forward for the chip industry. Different advanced packaging options — system-in-package, fan-outs, 2.5D, 3D-IC — have a... » read more

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