Managing Wafer Retest

Dealing with multiple wafer touchdowns requires data analytics and mechanical engineering finesse.


Every wafer test touch-down requires a balance between a good electrical contact and preventing damage to the wafer and probe card. Done wrong, it can ruin a wafer and the customized probe card and result in poor yield, as well as failures in the field.

Achieving this balance requires good wafer probing process procedures as well as monitoring of the resulting process parameters, much of it unseen by the outside world. The mechanical finesse and metallurgical complexity of wafer testing is mostly hidden from design, design for test (DFT), and even product engineers creating a product’s test strategy and test content. But that doesn’t make it any less critical. Without a carefully engineered and controlled wafer touchdown process, tests cannot be applied correctly. If the touch-down is too light, the test data will be incomplete. If it’s too hard, it can damage the tiny circuits.

“The least-understood impact of wafer probe is interaction between the wafer probe tip’s physical impact on active circuits below the pad/bump and upstream packaging processes,” said George Harris, vice president global test services at Amkor Technology.

Getting this wrong can lead to failures in the fab and in the field. “There’s all these potential long-term reliability issues associated with excessive probing,” explained Jerry Broz, senior vice president of technology development at International Test Solutions. “It could crack pads and affect bondability during assembly. Excessive probe mark depth and punch through could damage circuits under the pads resulting in an infantile failure or a walking wounded device.”

Due to product requirements, an IC device may receive multiple wafer tests at several temperatures. It also may be retested to recover yield. This often occurs due to improper wafer test cell setup or unexpected issues with the probe card, which requires a test floor operator/technician to investigate.

“Retest is valid and beneficial if it is related to a test setup problem, but not if the device is actually bad,” said Greg Prewitt, director of Exensio solutions at PDF Solutions. “Yield issues can point to bad probe cards, test plan setup problems, or device stability issues,”

By monitoring a variety of device test and equipment data, test factories can proactively manage the wafer test process to promptly identify yield issues and quickly determine if it’s a product or wafer test cell issue. The decisions made from such data provides inputs into the manufacturing execution system (MES). With yield management systems, fabless companies also monitor wafer test data for retests to more accurately discern a fab issue from a test operations setup issue.

Testing involves an electrical-mechanical connection. Mechanical actuation creates the physical contact that enables the electrical connection for transmitting power and signals to the device undertest. It is a given that the pad or bump will experience some deformation, such as scrub marks. Minimizing this deformation informs the engineering specifications for x, y, z prober control on the order of tens of microns.

Deformation also happens to the probe tips, making them less than ideal with each touchdown. To minimize this well-known impact, periodic cleaning of a probe card’s probe tips occurs. Prober equipment uses an automatic cleaning process which requires a clean of the probe tips after Y number touchdowns, where Y can range from 20 to 100 touchdowns.

Probe equipment, cleaning processing and manufacturing monitor data all support minimizing test cell issues. The probe card is where the test signal meets the device under test (DUT). Probe card manufacturers support multiple engineering requirements, including electrical test, operational efficiencies, and mechanical realities of the wafer probing process.

Wafer probe basics
When engineers generate ATPG patterns, architect a BiST scheme for a complex SoC, or develop analog-to-digital converter test content, they have an image of a wire between the DUT and ATE. What is not obvious is that it takes a tremendous amount of mechanical and metallurgical engineering to create that wire.

On a manufacturing test floor, technicians and operators insert wafer lots (typically 25 wafers), or packaged unit lots, into test cells. Those test cells are composed of the ATE, prober/handler, probe card/loadboard, and associated product test program. The test cell supports repetitive running of the test program on each DUT. To supply signals and power to the DUT, a metal-to-metal contact needs to be made between the DUTs pads/pin and interface hardware. For wafer test (sort or probe), this interface hardware is called a probe card, and prober equipment manages the physical process of touching a probe tip onto a die pad/bump.

Consider first the mechanical handling aspects of making a good contact.

“From a positional error stack-up this is an incredibly difficult problem,” said ITS’ Broz. “These pads are 40 by 50 microns square or smaller. Think about a one touch DRAM whole wafer probe card in which 120,000 probes touchdown on 120,000 pads, all at the same time with the same over travel. This can require a better than 25 micron planarity window across 300 millimeters in a prober, which is creating about 450 kgs of force (i.e., 1 to 2 grams of force per probe tip).”

Now, consider the metallurgy requirements. Depending upon the subsequent packaging technology, a probe card’s probe tip touches either a pad or a C4 bump, or micro-bump. For most wire-bond packages, the pad is made of aluminum or copper. In flip-chip packaging, C4 bumps range in their metallurgical compositions. While fabs and test floors have clean/semi-clean rooms, the people working in these facilities need oxygen and oxygen mixed with any metal creates an oxide. This oxide impairs the intermetallic contact necessary for an electrical test with each touchdown.

The necessity of breaking through the oxide requires the probe card to go beyond touching the pad/bump — typically as much as 50 microns. This over-travel results in a scrub mark on the pad/bump. Some product sectors requiring multiple temperature testing at wafer sort. To limit pad area damage, engineers aim to have the same scrub location touched. The smaller the scrub mark’s area, the less likely it will impact the die-to-package attach process.

Fig. 1: Wafer probe steps to create an intermetallic contact. Source: Semiconductor Engineering/Anne Meixner

Achieving high planarity across the probe card tips and probed die/dies reduces the amount of overtravel and hence reduces the scrub mark area and depth.

Planarity described the variation in the vertical distance (z direction) between the pads and the probe tips. Prober equipment typically uses optical alignment to assess planarity variation. The prober applies the overtravel distance only after all probes make a mechanical contact does, assuring a high-quality electrical contact.

Keeping everything aligned is an art, and things get more complicated with multiple temperature testing.

The most essential element in the probe card is the probe itself, and probe types range from cantilever to vertical springs and vertical MEMS. The design considerations include the product’s pad size and pitch, current capability, and temperature range. Probe material properties inherently impact the touchdown metallurgy, current carrying capability and coefficient of thermal expansion (CTE).

CTE directly impacts probe tip to pad/bump alignment, which ripples out to overall operation efficiency (OEE) of the test factory, as well as product reliability.


Fig. 2: DRAM probe card. Source: FormFactor.

“If you scrub too much there’s a reliability concern,” said Alan Liao, product marketing director for FormFactor’s probes business unit. “Most customers have between a 45-to-55 micron to 60-by-80-micron pad area (wire-bond product), and they want a minimum scrub mark. With multiple touchdowns each in different temperature environments, customer’s number one concern is touchdown accuracy. Temperature impacts the alignment process due to CTE differences between the probe card and wafer. Reaching the ideal thermal equivalent state can take two or more hours. No factory can wait that long, so then it becomes a tradeoff. Can you make the alignment good enough, plus or minus 5 microns, for example? You can apply some process design knowledge and use a pre-calculated probe position for different temperature conditions so you can meet alignment requirements as fast as possible.”

The forces applied to a wafer increase as multiple sites are added to the probe card. Those need to be monitored. Test results for open contacts indicate potential probing issues.

“At wafer test your probe card often has multiple test sites to enable parallel test — 4, 16, 32, or more. Having a homogeneous pressure across all the probes over all the die is a very critical parameter,” explained Stéphane Iung, senior manager applications in silicon lifecycle analytics at Synopsys. “If there exists inhomogeneous pressure, it can lead to contact failures on one or more test sites, so that’s really important to monitor. To compensate for that issue, to make sure that the contact quality is good, operators may supply higher over-travel. But over-travel can lead to pad damage, a kind of a pernicious side effect of trying to fix the first effect by higher over-travel. That potentially leads to degradation of the die.”

Monitoring and managing touchdowns quality
Contact failure is monitored by an electrical measurement of contact resistance.

Probe card designers, wafer test engineers, and test floor technicians assess the quality of the intermetallic contact by measuring contact resistance, or CRES. This parameter sets recipes for overtravel, cleaning cycles, and test monitor alarms for detecting issues with the test/prober set-up. When the contact resistance becomes too high it adversely impacts the signals between the ATE and the DUT as well as the power delivered to the DUT. This can result in either damage to the DUT or probe card and impairs distinguishing between good and bad die with the test program.

Fortunately, CRES can be measured in every die tested. It is calculated early in the wafer test program during the opens and shorts tests performed on I/Os. These tests check the contact integrity prior to powering up and protect the DUT, ATE and probe card from damage. Most I/Os have ESD protection diodes, which test engineers to use for their contact resistance measurement. The most common way is to source two different currents, measure the resulting voltages to give you the familiar slope of Ohm’s law (i.e. R=V/I). CRES can be measured per signal pin.

Over multiple touchdowns, wafer test processes can monitor the mean and standard deviation of CRES. Test floor operations use CRES monitoring as a manufacturing statistical process control parameter. In developing probing technology a module engineer sets a CRES specification per semiconductor process technology. Now each time a probe card touches a die it gets a little bit dirty, and dirt increases contact resistance. To maintain the CRES target periodic cleaning is performed.

“Probe cards used in wafer-sort range from very basic designs to highly engineered ‘correct by construction’ technologies that are built using semiconductor-like 2D and 3D MEMS processes,” said Broz. “No single probe or probe card technology solution fits to address all the device testing requirements. However, all probing solutions (no matter how advanced) must be cleaned during wafer test to maintain their performance.”

With multiple probes on the same die, engineers want each subsequent touch-down to touch down in the same location. This minimizes the impact on the wire-bond die attach process. The more untouched pad area, the more successful the wire-bond attach process. This is so important that industries with high sensitivity to reliability-related failures, such as automotive, restrict the number of wafer touch-downs.

Thus monitoring factors that cause high contact failures is part of every test floor operations.

To mitigate the management of the probing process a larger number of parameters to monitor and control testify to the mechanical electrical engineering complexity of the process. Amkor’s Harris listed the following:

  • Re-probe count;
  • Stepping beyond exclusion zones;
  • Chuck motion accuracy — X, Y, and Z and rotation;
  • Electrical contact resistance and site to site variations;
  • Physical dimensions of the probing material (length/width size min/max);
  • Planarity;
  • Alignment;
  • Angles of incidence, and
  • Spring characteristics over time.

“These control parameters are actively measured using prior and post-test processes, as well as in-situ and real-time in the test processes with historical SPC limits and predictive analytic methodologies,” said Harris.

With these parameters, test floor engineers and technicians monitor probe card health for off-line maintenance because unexpected replacement is expensive — and not just in dollars.

“If they have to replace the card, that’s where it gets expensive,” said Keith Schaub vice president of technology and strategy at Advantest America. “More importantly, this impacts time-to-market because now they have to order this probe card. It has to be assembled. It has to be calibrated. It has to be verified. This all takes time.”

The order to ship time is commonly six months. This motivates maintaining probe card health. Automatic cleaning on the test cell is one maintenance component. The other is regular inspections with a probe card analyzer. Test floor operations with a high mix of products can use the test cell change over to perform regular inspection and maintenance.

“With a probe card analyzer, a technician can look for both electrical and mechanical changes,” said Darren James, technical account manager at Onto Innovation. “This involves electrically checking resistance of the connects, checking resistor and capacitor values on the probe card, checking relays. It also involves mechanically checking the location of the probe tip in X, Y, and Z, both free hanging and at over-travel, checking probe force, checking probe planarity for no bused pins (an electro-mechanical test).”

As test floors innovate with Industry 4.0 technologies, the ability to proactively identify impending problematic probe card can improve both operational efficiencies and test program measurement accuracy.

“Degraded yield/throughput is indicative of a failing or damaged probe card or load board,” said PDF Solutions’ Prewitt. “Without a data analytics solution in place, the degradation can persist for an extended period of time before it is noticed or resolved through standard maintenance procedures.”

As with the assembly process, the mechanical and metallurgical challenges in wafer probing require high-quality inter-metallic contacts that guarantee the flow of electrons. But for a package this is a one-time connection, while in wafer probing this needs to occur many times. For a die, this may be as few as three or as many as six times, and it can involve multiple temperatures and re-probing due to poor electrical contact. For a probe tip, it’s on order of tens of thousands of touch-downs.

Engineering teams on the test floors actively manage the wafer touch-down process and monitor multiple parameters from the test equipment and wafer test results. With analytic platforms for both test and factory equipment, data engineers and technicians proactively can respond to degrading contact resistance, use intelligent probing systems to meet touch-down limits, and reduce damage to product and probe cards.


yieldWerx says:

Wafer retest method is indeed a sensitive and highly useful method used in the semiconductor manufacturing industry. This technical method reduces the intervention of manual engineers which further reduces the risk of manual misjudgment. This also provides many beneficial effects for semiconductor yield management.

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