tag: probe tips

3D Connection Artifacts In PDN Measurements
By Cadence - 28 Feb, 2024 - Comments: 0

Authors: Ethan Koether, Amazon; Kristoffer Skytte, John Phillips, Shirin Farrahi, Cadence; Joseph Hartman, Oracle; Sammy Hindi, Ampere Computing Inc.; Mario Rotigni, STMicroelectronics; Gustavo Blando, Istvan Novak, Samtec From a simulation stand-point, we have covered several important topics that users must consider in detail to get accurate low frequency simulation results. We investigate... » read more

Test Connections Clean Up With Real-Time Maintenance
By Anne Meixner - 08 Nov, 2022 - Comments: 0

Test facilities are beginning to implement real-time maintenance, rather than scheduled maintenance, to reduce manufacturing costs and boost product yield. Adaptive cleaning of probe needles and test sockets can extend equipment lifetimes and reduce yield excursions. The same is true for load board repair, which is moving toward predictive maintenance. But this change is much more complicate... » read more

Cleaning Up During IC Test
By Anne Meixner - 06 Jul, 2021 - Comments: 2

Test is a dirty business. It can contaminate a unit or wafer, or the test hardware, which in turn can cause problems in the field. While this has not gone unnoticed, particularly as costs rise due to increasing pin and ball density, and as more chips are bundled together in a package, the cost of dirt continues to be a focus. Cleaning recipes for test interface boards are changing, and analy... » read more

Managing Wafer Retest
By Anne Meixner - 19 May, 2021 - Comments: 1

Every wafer test touch-down requires a balance between a good electrical contact and preventing damage to the wafer and probe card. Done wrong, it can ruin a wafer and the customized probe card and result in poor yield, as well as failures in the field. Achieving this balance requires good wafer probing process procedures as well as monitoring of the resulting process parameters, much of it ... » read more

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