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Cleaning Up During IC Test


Test is a dirty business. It can contaminate a unit or wafer, or the test hardware, which in turn can cause problems in the field. While this has not gone unnoticed, particularly as costs rise due to increasing pin and ball density, and as more chips are bundled together in a package, the cost of dirt continues to be a focus. Cleaning recipes for test interface boards are changing, and analy... » read more

Managing Wafer Retest


Every wafer test touch-down requires a balance between a good electrical contact and preventing damage to the wafer and probe card. Done wrong, it can ruin a wafer and the customized probe card and result in poor yield, as well as failures in the field. Achieving this balance requires good wafer probing process procedures as well as monitoring of the resulting process parameters, much of it ... » read more