Week In Review: Design, Low Power

By Karen Heyman - 26 May, 2023 - Comments: 0

Cadence bought Pulsic, a U.K.-based developer of place-and-route tools for custom digital and analog. The acquisition follows a previous acquisition attempt by a Chinese firm in August 2022, which was blocked by the U.K. government. At the G7 Summit in Japan, IBM announced a 10-year, $100 million initiative with the University of Tokyo and the University of Chicago to develop a quantum-centr... » read more

Week In Review: Design, Low Power

By Marie C. Baca - 26 Aug, 2022 - Comments: 0

Quantum computing Baidu introduced a 10-qubit quantum computer called Qianshi and what it described as “the world's first all-platform quantum hardware-software integration solution that provides access to various quantum chips via mobile app, PC, and cloud.” The company said it has also completed the design of a 36-qubit quantum chip. Scientists said “levitating” nanoparticles co... » read more

Week In Review: Design, Low Power

By Jesse Allen - 24 Jun, 2022 - Comments: 0

RISC-V RISC-V International announced four new specification and extension approvals. Efficient Trace for RISC-V defines an approach to processor tracing that uses a branch trace. RISC-V Supervisor Binary Interface architects a firmware layer between the hardware platform and the operating system kernel using an application binary interface in supervisor mode to enable common platform services... » read more

Week In Review: Design, Low Power

By Jesse Allen - 05 Feb, 2021 - Comments: 0

Tools & IP Synopsys is joining Microsoft in the U.S. Department of Defense's Rapid Assured Microelectronics Prototypes (RAMP) program to support the development of IC hardware and workflow prototypes that incorporate Synopsys' assured design and manufacturing flows into Microsoft Azure. The RAMP program aims to bring commercial capabilities and speed to the development of semiconductors fo... » read more

The Week In Review: Design

By Jesse Allen - 17 Nov, 2017 - Comments: 0

Tools Aldec released the latest version of its Riviera-PRO verification platform, adding QEMU Bridge to enable hardware/software co-simulation of designs intended to run on SoC FPGAs. Other features include improved performance when using code containing many inline randomized calls and up to 29% faster simulation speed of UVM. Pulsic added new features to its Unity Bus Planner for planning... » read more

Analog’s Day Of Reckoning

By Brian Bailey - 16 Jun, 2015 - Comments: 0

The numbers being touted by the semiconductor industry for IoT edge devices are staggering. How they are going to be used, who will make them, or indeed who will make money from them are much less certain. The industry seems to be clear about the content of these devices. A small processor, some flash memory or possibly even some of the new memory technologies that are coming along, a radio ... » read more

The Road Ahead For 2014: Tools

By Brian Bailey - 30 Jan, 2014 - Comments: 0

In the third and final part of this predictions series we see the natural conclusion of market shifts that are driving changes in semiconductors, and which in turn drive the tools and IP needed to create those systems. To be expected, the changes fall into a few areas: New tools, techniques and changes required for smaller geometries; A migration to higher-levels of abstraction and the... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: Pulsic

Week In Review: Design, Low Power

Week In Review: Design, Low Power

Week In Review: Design, Low Power

Week In Review: Design, Low Power

The Week In Review: Design

Analog’s Day Of Reckoning

The Road Ahead For 2014: Tools