Week in Review – IoT, Security, Auto

By Jeff Dorsch - 21 Jun, 2019 - Comments: 0

Products/Services Arteris IP reports Achronix Semiconductor licensed the Arteris FlexNoC interconnect IP for its new Speedster7t line of FPGAs. Speedster7t features ASIC-like performance, FPGA adaptability, and enhanced functionality to streamline design. "Our new Speedster7t FPGA family requires extremely high on-chip bandwidth and advanced dataflow arbitration to make possible ASIC-class mac... » read more

Week In Review: Design, Low Power

By Jesse Allen - 21 Jun, 2019 - Comments: 0

ON Semiconductor completed its $946 million acquisition of Quantenna Communications, a San Jose-based company that specializes in Wi-Fi chips and software. Aldec introduced automatic UVM register generation to its Riviera-PRO verification platform. Riviera-PRO can now accept a CSV file or IP-XACT register description as an input and, working at the Register Abstraction Layer (RAL) of UVM, ou... » read more

Week In Review: Design, Low Power

By Jesse Allen - 29 Mar, 2019 - Comments: 0

ON Semiconductor will acquire Quantenna Communications for $24.50 per share in an all cash transaction, representing an equity value of approximately $1.07 billion and enterprise value of approximately $936 million. Quantenna, a maker of Wi-Fi chipsets, was founded in 2006 and went public in late 2016. Tools & IP Achronix completed testing and is now demonstrating the 112 Gbps SerDes th... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

tag: Quantenna Communications

Week in Review – IoT, Security, Auto

Week In Review: Design, Low Power

Week In Review: Design, Low Power

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