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Week In Review: Design, Low Power

PCIe 6.0; automatic UVM register generation; what’s in Achronix’s latest FPGA.

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ON Semiconductor completed its $946 million acquisition of Quantenna Communications, a San Jose-based company that specializes in Wi-Fi chips and software.

Aldec introduced automatic UVM register generation to its Riviera-PRO verification platform. Riviera-PRO can now accept a CSV file or IP-XACT register description as an input and, working at the Register Abstraction Layer (RAL) of UVM, output files as RTL register models, C headers and HTML. Additionally, libraries containing pre-compiled source code compliant with the latest versions of UVM (IEEE 1800.2-2107) and UVVM (2018.12.03), plus documentation and examples, have been added to facilitate test bench creation.

PCI-SIG announced PCIe 6.0, which will double the data rate to 64 GT/s raw bit rate and provide up to 256 GB/s with a x16 configuration. Utilizing PAM-4 encoding, it will include low-latency Forward Error Correction (FEC) with additional mechanisms to improve bandwidth efficiency as well as maintain backwards compatibility with previous PCIe generations. The PCIe 6.0 specification is actively targeted for release in 2021.

Achronix selected Moortec’s 7nm Embedded Temperature Sensor IP to optimize performance and increase reliability for the company’s Speedster7t FPGAs. Achronix said that Moortec’s in-chip temperature sensors enabled them to overcome a number of thermal challenges associated with advanced node design. Achronix also licensed Arteris IP’s FlexNoC interconnect IP for the Speedster7t FPGA family, which is designed for AI/ML and high-bandwidth workloads. Achronix noted this was the optimal interconnect to meet the demands of extremely high on-chip bandwidth and advanced dataflow arbitration. Plus, Achronix said it is using Rambus’ GDDR6 PHY in the Speedster7t FPGA family.

Acacia Communications adopted Cadence’s Palladium Z1 Enterprise Emulation Platform for the development of its DSP ASICs for optical networking applications. Using the cloud-based model, Acacia was able to compile the full multi-hundred-million gate digital content for the platform locally, upload the image, and run tests of thousands of frames across many modes of operation in overnight regressions via the Palladium Cloud. Acacia cited the ability of the platform’s ability to execute synthesizable models at speeds greater than classic simulation.

Airbus Defence and Space adopted ANSYS’ embedded software solution to develop an advanced Unmanned Aerial Vehicle (UAV) that will be engineered for speed, safety and affordability. A strategic partnership between the two companies will focus on creating a solution for safety-critical flight controls with sophisticated AI, aiming at autonomous flight by 2030.

Western Digital, PlatformIO Labs, and SiFive teamed up to extend the PlatformIO vendor-agnostic embedded development platform to include new tools to provide an end-to-end, open environment, including development for RISC-V. “By teaming up with PlatformIO, we are bringing the entirety of its multi-architecture embedded design environment, including debug and trace, to the open-source community. With deep libraries and automated support already built-in, this will allow programmers to easily transition among development platforms, including RISC-V,” said Martin Fink, chief technology officer, Western Digital. The collaboration allows software programmers developing for RISC-V and other architectures to use PlatformIO’s previously paid PlatformIO Plus features at no cost. Western Digital also updated its open-source RISC-V SweRV Core, adding faster divide and fetch functions, the incorporation of I/O timing control, better error correction capabilities, and multi-core debug improvements, as well as updates to its OmniXtend cache-coherent fabric.

Events
ES Design West: July 9-11 in San Francisco, CA. The new conference focuses on IP, EDA, embedded software, design services, and infrastructure. Along with a dedicated conference track, there will be presentations and panels on the show floor. Presented by the ESD Alliance, the conference is co-located with SEMICON West.



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