Chip Industry Week In Review


By Jesse Allen, Karen Heyman, and Liz Allan Japan's Rapidus and the University of Tokyo are teaming up with France's Leti to meet its previously announced mass production goal of 2nm chips by 2027, and chips in the 1nm range in the 2030s. Rapidus was formed in 2022 with the support of eight Japanese companies — Sony, Kioxia, Denso, NEC, NTT, SoftBank, Toyota, and Mitsubishi's banking arm, ... » read more

Chip Industry Week In Review


By Susan Rambo, Karen Heyman, and Liz Allan The Biden-Harris administration designated 31 Tech Hubs across the U.S. this week, focused on industries including autonomous systems, quantum computing, biotechnology, precision medicine, clean energy advancement, and semiconductor manufacturing. The Department of Commerce (DOC) also launched its second Tech Hubs Notice of Funding Opportunity. ... » read more

Week In Review: Design, Low Power


Qualcomm, NXP, Infineon, Nordic, and Bosch are jointly investing in a new RISC-V company, to be formed in Germany, that will speed up RISC-V’s adoption in commercial products. The company will be “a single source to enable compatible RISC-V based products, provide reference architectures, and help establish solutions widely used in the industry,” according to a press release. The co... » read more

New Age Solution For Data Integrity And Authenticity


With the advent of faster processing chips, the rate of data transfer has increased enormously. Be it artificial intelligence (AI), the Internet of Things (IOT), compute intensive analytics, or cloud computing, the demand for processing data in a fraction of a second is huge. Chips with superfast computing capabilities are used in applications where malfunctions can be life threatening, such as... » read more

Week In Review: Design, Low Power


RISC-V RISC-V International announced four new specification and extension approvals. Efficient Trace for RISC-V defines an approach to processor tracing that uses a branch trace. RISC-V Supervisor Binary Interface architects a firmware layer between the hardware platform and the operating system kernel using an application binary interface in supervisor mode to enable common platform services... » read more

PCIE 6.0 Vs 5.0 — All You Need To Know


While the PCI-SIG has announced that the release of the PCI Express® 6.0 (PCIe 6.0) specification should arrive in 2022, Rambus is already addressing the needs of early adopters looking for the most advanced PCIe 6.0 IP solutions for their SoC and ASIC designs. You can find all about the new generation specification in the article below. Click here to read more. Article or... » read more

Week In Review: Design, Low Power


Nvidia again made its case for acquiring Arm to the UK's Competition and Markets Authority (CMA). “Arm is a private for-profit business at a crossroads. After acquiring Arm several years ago, SoftBank increased Arm’s headcount, hoping to spur long-term growth in several markets, including data center and personal computer, long dominated by Intel and x86. SoftBank’s investment phase has c... » read more

Week In Review: Design, Low Power


ON Semiconductor completed its $946 million acquisition of Quantenna Communications, a San Jose-based company that specializes in Wi-Fi chips and software. Aldec introduced automatic UVM register generation to its Riviera-PRO verification platform. Riviera-PRO can now accept a CSV file or IP-XACT register description as an input and, working at the Register Abstraction Layer (RAL) of UVM, ou... » read more

Week In Review: Design, Low Power


M&A NXP will acquire Marvell's Wi-Fi Connectivity business in an all-cash, asset transaction valued at $1.76 billion. The deal includes the Wi-Fi and Bluetooth technology portfolios and related assets; the business employs approximately 550 people worldwide. The deal is expected to close by calendar Q1 2020. Tools Cadence unveiled a data center-optimized FPGA-based prototyping system, ... » read more

The Week In Review: Design


Tools Mentor added new tools to its high-level synthesis portfolio. The DesignChecks tool helps find bugs during coding with a static mode that performs very fast linting-like checks of the code and a formal mode that uses a formal engine for a more exhaustive proof of issues. The synthesis-aware Coverage tool measures code coverage for C++ signoff and fast closure of synthesized RTL. It sup... » read more

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