Pain Management


In part one of this series, the focus was on overlapping and new pain points in the semiconductor flow, from initial conception of what needs to be in a chip all the way through to manufacturing. Part two looks at how companies are attempting to manage that pain. It’s no secret that [getkc id="81" kc_name="SoC"]s are getting more complicated to design, debug and build, but the complexity i... » read more

Blog Review: April 2


Mentor’s Nazita Saye compares roadway roundabouts to networked systems. One roundabout works fine, but add in a bunch of them and you have a massive traffic jam. How many roundabouts are in your design? Cadence’s Richard Goering interviews Stan Kroliskoski, chair of the IEEE Design Automation Standards Committee, about four working groups on EDA standards and what’s ahead. Speaking ... » read more

The Week In Review: Design


Tools Synopsys rolled out a major new release of its place and route tool, the centerpiece of its physical design platform, offering up to 10X improvement in speed—a combination of 5X faster implementation and 2X larger capacity. Co-CEO Aart de Geus called it the most significant product in the company’s history. Synopsys also rolled out an AMS verification platform to accelerate regres... » read more

The Next Bigger Things


When the Internet of Things really started making headlines several years ago—the concept had been around since at least the early 1990s—the assumption was that most of the semiconductors involved in sensing and communicating would be simple, highly limited, and developed using older technology. As the concept evolves and grows, however, it’s beginning to take on a whole new texture. R... » read more

Blog Review: March 5


ARM’s Lori Kate Smith has discovered an unusual electronic billboard advertisement for shampoo on a train platform in Sweden. Watch what happens when the train goes by. Mentor’s J. VanDomelen puts a magnifying glass on the U.S. Defense budget and where the money is going. Times have changed with technology. Who needs soldiers? Cadence’s Brian Fuller interviews Mindtree CTO S. Janaki... » read more

EDA Hungers For Growth


Look at the top line numbers provided by the EDA industry consortium (EDAC) and it appears as if the industry is doing well. In 2010, revenue was $5.285 billion. That number increased to $6.218 billion in 2011, and again to $6.529 billion in 2012, a 9.5% annual growth rate that would satisfy most investors. But the numbers do not tell the whole story. There is an interesting divide growing betw... » read more

The Next Big Threat: Power And Performance


In the shiny world of consumer electronics and powerful computers, taking a grinder to the outside of a package may sound more like safecracking than sophisticated electronic code hacking. The reality is there is more in common than most semiconductor companies would like to admit, and the starting point often is just as crude. To no small extent, systems on chip have become miniature safes.... » read more

Straight Talk On 3D TSVs


By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss 3D device challenges and applications with John Lau, a fellow at the Industrial Technology Research Institute (ITRI), a research organization in Taiwan. SMD: What is ITRI doing in 3D TSVs? Lau: At ITRI we have developed the world’s first Applied Materials’ 300mm (3D TSV) integration line. The line was comple... » read more

Designing into A Foundry Low-Power High-k Metal Gate 28nm CMOS Solution


28nm Super Low Power is the low power CMOS offering delivered on a bulk silicon substrate for mobile consumer and digital consumer applications. The 28nm process technology is slated to become the foundation for a new generation of portable electronics that are capable of handling streaming video, data, voice, social networking and mobile commerce applications. To view this white paper, clic... » read more

The Challenges Of 28nm HKMG


28nm Super Low Power (28nm-SLP) is the low power CMOS offering delivered on a bulk silicon substrate for mobile consumer and digital consumer applications. This technology has four Vt's (high, regular, low and super low) for design flexibility with multi-channel length capability and offers the ultimate in small die size and low cost. Multiple SRAM bit cells for high density and high-performanc... » read more

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