tag: Rambus

Blog Review: Feb. 5
By Jesse Allen - 05 Feb, 2025 - Comments: 0

Cadence's Rajneesh Chauhan explores the extended metadata feature in CXL 3.1, which helps systems manage memory and devices more effectively by sending extra information along with memory transactions to provide more context about what's happening during these transactions. Siemens' Bianca Ward recommends semiconductor companies combat rising production costs by leaning into digitalization a... » read more

The Road To Super Chips
By Ed Sperling - 27 Jan, 2025 - Comments: 0

Reticle size limitations are forcing chip design teams to look beyond a single SoC or processor in order to achieve orders of magnitude improvements in processing that are required for AI. But moving data between more processing elements adds a whole new set of challenges that need to be addressed at multiple levels. Steve Woo, distinguished inventor and fellow at Rambus, examines the benefits ... » read more

Automotive OEMs Face Multiple Technology Adoption Challenges
By Ann Mutschler - 22 Jan, 2025 - Comments: 0

Experts At The Table: The automotive ecosystem is in the midst of significant change. OEMs and tiered providers are grappling with how to deal with legacy technology while incorporating ever-increasing levels of autonomy, electrification, and software-defined vehicle concepts, just to name a few. Semiconductor Engineering sat down to discuss these and other related issues with Wayne Lyons, seni... » read more

Choosing The Right Memory Solution For AI Accelerators
By Tim Messegee - 16 Jan, 2025 - Comments: 0

To meet the increasing demands of AI workloads, memory solutions must deliver ever-increasing performance in bandwidth, capacity, and efficiency. From the training of massive large language models (LLMs) to efficient inference on endpoint devices, choosing the right memory technology is critical for chip designers. This blog explores three leading memory solutions—HBM, LPDDR, and GDDR—and t... » read more

Cryptography Does Not Equal Security
By Bart Stevens - 09 Jan, 2025 - Comments: 0

At Rambus, we often receive RFIs, RFPs and RFQs for security silicon IP cores to be used in our customer’s next semiconductor product. Such requests often contain a long shopping list of required cryptographic algorithms, their modes of operation, their key lengths or strengths and performance and sizing requirements. Depending on the target segment, additional requirements such as robustness... » read more

Edge And IoT Security Turning A Corner
By Ed Sperling - 09 Jan, 2025 - Comments: 0

Security is beginning to improve for a wide range of IoT and edge devices due to better tools, the implementation of new standards and methodologies, and an increasing level of collaboration and communication across different market segments that in the past had little or no interaction. Until recently, many vendors in cost-sensitive markets offered the bare minimum of security. To make matt... » read more

How Software-Defined Vehicles Change Auto Chip Design
By Adam Kovac - 09 Jan, 2025 - Comments: 0

The shift to software-defined vehicles is changing nearly every aspect of automotive design, from what hardware is added into vehicles, when it gets added, and what gets left behind. Moving key features to software rather than hardware allows carmakers to bring new features to market faster, at a lower cost, and to modify those features more quickly. It is also expected to drive up the value... » read more

Auto Ecosystem Begins Shift To Software-First
By Ann Mutschler - 30 Dec, 2024 - Comments: 0

Experts at the Table: The automotive ecosystem is in the midst of an intense evolution as OEMs and tiered providers grapple with how to deal with legacy technology while incorporating ever-increasing levels of autonomy, electrification, and software-defined vehicle concepts. Semiconductor Engineering sat down to discuss these and other related issues with Wayne Lyons, senior director for the au... » read more

Chip Industry Week In Review
By The SE Staff - 13 Dec, 2024 - Comments: 0

The 2024 IEEE International Electron Devices Meeting (IEDM) was held this week, prompting a number of announcements from: imec: Proposed a new CFET-based standard cell architecture for the A7 node containing two rows of CFETs with a shared signal routing wall in between, allowing standard cell heights to be reduced from 4 to 3.5T, compared to single-row CFETs. Integrated indium pho... » read more

Why PCIe And CXL Are Essential Interconnects For The AI Era
By Lou Ternullo - 12 Dec, 2024 - Comments: 0

As the demand for AI and machine learning accelerates, the need for faster and more flexible data interconnects has never been more critical. Traditional data center architectures face several challenges in enabling efficient and scalable infrastructure to meet the needs of emerging AI use cases. The wide variety of AI use cases translate into different types of workloads. Some require high ... » read more

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