AI-Defined Vehicles Increase Pressure On Auto Ethernet Reliability


Key Takeaways: For AI-defined vehicles and onboard agentic AI, Automotive Ethernet provides high bandwidth for sensor data fusion, TSN ensures low latency and synchronization for real-time decisions, and MACsec secures the data link. Time-sensitive networking (TSN) is an essential protocol for ensuring 10BASE-T1S delivers data to where it needs to go on time. Still, it becomes less esse... » read more

Securing Terabit Ethernet For AI: Where MACsec, IPsec, And UET TSS Each Fit (And Why You Need More Than One)


As AI and HPC systems scale, the network has become both a critical enabler of performance and a rapidly expanding attack surface. The shift from rack-scale compute to cluster- and data center-scale AI infrastructure means that data is no longer confined to a single chip, board, or even system. Instead, it moves continuously across hundreds, or thousands, of endpoints, often at aggregate bandwi... » read more

Chip Industry Week In Review


ECTC Panel-level packaging, hybrid bonding, new substrates, and fine-pitch interconnects topped the list of advanced packaging technologies at ECTC this week. Among the announcements: ASE launched an automated 310mm × 310mm panel-level packaging production line. Expected to enter production in the first half of 2027, the line is compatible with FOCoS and FOCoS-Bridge pa... » read more

Chip Industry Week in Review


Global The U.S. created a licensing path for Nvidia H200 shipments in January and has since approved sales to 10 Chinese companies, but so far no shipments have been confirmed, reports Reuters. With a looming end-of-year expiration, SIA, SEMI, and other business groups are urging Congress to extend the US semiconductor tax credit and expand it to cover semiconductor design and other act... » read more

SOCAMM2: Bringing LPDDR5X Benefits To AI Servers


The rapid scaling of artificial intelligence is reshaping nearly every dimension of data center design. While much of the focus has been on GPUs, accelerators and advanced packaging, another constraint is emerging as equally critical: power. As AI models grow larger and more complex, power consumption, not raw compute, is increasingly the limiting factor in system scalability. Modern AI work... » read more

Flash Getting Stacked High-Bandwidth Version


Key takeaways: A new HBF 3D flash stack is similar to HBM for use in AI processing. HBF capacity will be much higher, allowing static storage of AI model weights, with optimized read speed. Samples are due out later this year, with accelerators featuring it coming out next year. AI inference using modern models requires billions of parameters, and moving them to where they c... » read more

Chip Industry Week In Review


Manufacturing ASE and WUS are jointly building a ~$1.1B advanced packaging hub in Kaohsiung, Taiwan, for fan-out chip-on-substrate (FOCoS) and flip-chip ball grid array (FC BGA) technologies. The new site is expected to be completed by September 2029. SpaceX filed documents for a “Terafab” semiconductor manufacturing and computing facility at Gibbons Creek Reservoir in Texas, with a... » read more

Securing Chiplet-Based Platforms: Distributed Trust With Centralized Authority


In previous blogs, From Monolithic SoCs to Chiplets: A New Hardware Security Paradigm, and Developing a Security Framework for Chiplet-based Systems, we discussed why chiplets change the game from a security perspective, and why security must be addressed at a platform-level in a chiplet-based system. In a monolithic device, trust is often implicitly bounded by the die itself: sensitive asse... » read more

Next-Gen Batteries Require Impedance Data And Active Balancing


Key Takeaways Electric vehicles and energy storage systems using LFP batteries require more sophisticated diagnostic methods because they exhibit very flat cell voltages across various charge levels, making it harder to estimate usable energy. Battery management systems are leveraging new components, AI/ML, digital twins, and other techniques to get more accurate, real-time data, includ... » read more

Designing Chips In The Context Of Rapidly Evolving AI


Key Takeaways: Agentic edge AI drives long-lived, tool-mediated loops with variable demands for compute, tokens, and memory. Edge PPA is dominated by memory hierarchy and data movement, forcing tight feature triage and robust RAS. Rapid model churn (multimodal, MoE, new formats) requires programmable, headroom-rich compute, interconnect, and runtime. Experts At The Table: Ch... » read more

← Older posts Newer posts →