tag: reuse

Adaptive Fuzzing Framework that Reuses Tests from Prior Processors (Texas A&M, TU Darmstadt)
By Technical Paper Link - 10 Dec, 2025 - Comments: 0

A new technical paper titled "ReFuzz: Reusing Tests for Processor Fuzzing with Contextual Bandits" was published by researchers at Texas A&M University and TU Darmstadt. Abstract "Processor designs rely on iterative modifications and reuse well-established designs. However, this reuse of prior designs also leads to similar vulnerabilities across multiple processors. As processors grow... » read more

PCB Modularity Reuse and Scale
By Cadence - 03 Sep, 2025 - Comments: 0

In a world of shrinking timelines and growing complexity, modularity isn't a luxury—it's a necessity. This eBook explores how PCB designers can move from one-off designs to scalable systems by rethinking schematics, embracing abstraction, and designing for reuse. What you’ll learn: How modular thinking drives scalability Why abstraction accelerates hardware design How to ap... » read more

IC Manufacturing Targets Less Water, Less Waste
By Anne Meixner - 16 Nov, 2023 - Comments: 0

Fabs, OSATs, and equipment makers are accelerating their efforts to consume less water while recycling more material waste in a trend toward better sustainability. With chips, sustainability is heavily focused on carbon emissions, and energy consumption is a significant contributor. But there is an equal effort underway to reduce water consumption and pollution. Across the globe, the number ... » read more

Can AI Write RTL?
By Brian Bailey - 01 May, 2023 - Comments: 1

Just a few months ago, generative AI was just a promise about what would be possible in the future. Today, nearly everyone with an ounce of curiosity has tried ChatGPT. Most people appear to be somewhat impressed with what it can do, but at the same time see the limitations that it has. As Dean Drako, founder of several companies, told me: "Recently, I needed to write a patent. I described t... » read more

Time For FMEDA Reuse?
By Stefano Lorenzini - 07 Jul, 2022 - Comments: 0

How do designers quantify safety in electronic systems? Through one or more tables called Failure Modes, Effects and Diagnostic Analysis – FMEDA. In fact, an FMEDA does not have to be a table; it could be manifested in scripts or some other form, but a table is the easiest way to think of this information. Think of an FMEDA for an IP, as the concept extends easily to a system-on-chip (SoC). T... » read more

Traceability Is Not My Problem (Is It?)
By Paul Graykowski - 21 Jun, 2022 - Comments: 0

What is all the fuss about traceability? If it is that important, should it be handled by a compliance group? Delegating to a separate team would be the preference for most design and verification team members, but it is not possible in this case. Traceability stops short of a big brother organization constantly looking over the shoulders of the development team. The more reasonable approach is... » read more

Building A Safety Verification Flow
By Ed Sperling - 24 Mar, 2020 - Comments: 0

Sal Alvarez, senior manager of application engineering at Synopsys, explains how safety verification differs from functional verification, what changes with failure mode effects analysis, and how to determine and verify the effectiveness of safety features. » read more

Can You Afford To Waste Time On Your Next Design Project?
By Amit Varde - 09 Jan, 2020 - Comments: 0

Let’s be honest: engineers are asked to perform miracles every day, and they almost always deliver. They are challenged to invent the future in the form of newly sophisticated, powerful and highly functional systems-on-chips and systems. On top of this, they’re required to do so with an increasingly complex array of tools and re-use increasing amounts of IP to speed time-to-market. Oh, and ... » read more

Writing Reusable UPF For RTL And Gate-Level Low Power Verification
By Durgesh Prasad - 08 Aug, 2019 - Comments: 0

By Durgesh Prasad, Jitesh Bansal and Madhur Bhargava The Unified Power Format (UPF) is used to specify the power intent of a design. Once written, the UPF file is applied at every stage of the design cycle — starting with the RTL, then the gate-level, and finally during place and route. A major problem is that the UPF needs to be refined or modified at every stage to keep it compatible ... » read more

Secret Sauce To Make Design Reuse A Reality
By Ranjit Adhikary - 04 May, 2017 - Comments: 0

In a globally competitive landscape, IP reuse and effective team collaboration play a crucial role in product success. But if one considers the complex dynamics of all the recent advances in technology, the insatiable appetite for consumer electronics coupled with the design cost and time-to-market pressures on designers, one would not be unjustified in assuming that the problem of design reuse... » read more

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