Can You Afford To Waste Time On Your Next Design Project?

Let’s be honest: engineers are asked to perform miracles every day, and they almost always deliver. They are challenged to invent the future in the form of newly sophisticated, powerful and highly functional systems-on-chips and systems. On top of this, they’re required to do so with an increasingly complex array of tools and re-use increasing amounts of IP to speed time-to-market. Oh, and so do so on time and on budget.

The state of silicon and IP design today is complex, with a typical project composed of several design libraries, from mid to low-level, which are stitched together to get a top-level representation of a design. This sounds easy, but within the details lie land mines. Let me illustrate this with a recent experience I witnessed.

My customer is a design manager, Hank (not his real name), who has a reputation for his expertise with mixed-signal IPs. His company produces ICs. They get designed into several consumer electronics applications, such as toys. For such seasonal products, it is vitally important that the product gets a design win with the toy manufacturer early enough to translate it into a large production order. Slipping a tape-out schedule can have far-reaching implications on the company’s bottom line.

Hank’s company optimizes its design schedule by reusing the IP blocks they have previously developed. Hank is responsible for developing a PLL (phase-locked loop). Typically, his IP gets used in quite a few ICs that his company releases every year.

As in previous years, Hank was developing a PLL for several internal customers – all with slightly different requirements but all with a strict deadline for their tape-out! All was going well even as the tape-out deadlines were fast approaching. That’s every design manager’s dream! Almost all experienced managers would now say, “Too good to be true!” And yes, it was too good to be true! It turns out that one of the consumers reported that the power consumption of the PLL needed to be optimized further. So Hank and his team traced the issue to some of the low-level logic cells in his PLL module. The fix would affect almost all his internal customers rushing towards their deadlines.

Hank was faced with two challenges when he called us at ClioSoft.

First, who were all the consumers that were using his PLL, and what release were they currently using? Hank needed an accurate report so that he could go and warn these IC design teams of the upcoming change as well as understand the impact of this change for them and if he needed to prioritize power optimization over the other tasks planned for the PLL IP.

Hanks’ second challenge was finding out which cells in the PPL library would need characterization if the low-level logic cells were to be optimized. Hank intended to use this list to plan which members of his team need to be assigned to the low-power fix.

Luckily for Hank and his company, he was using the ClioSoft SOS7’s referencing feature. One of the critical benefits of this feature is that it reports a list of consumer projects using the PLL and precisely what release of the PLL they were using, Figure 1. Hank was able to immediately meet with the design managers for the respective projects and understand the impact of the issue on their product and tape-out schedule. In due course, Hank realized that power optimization was not as critical to most of his other consumers. He was able to assign priority and get over his challenge reasonably quickly and without raising major red flags.

Figure 1.

However, his second challenge was still unresolved: The one consumer who had reported the issue still needed the optimization. Hank still needed to understand the impact of changing low-level logic cells within the PLL library. Hank’s PLL design is a self-contained hard macro using the Cadence OA database. ClioSoft’s SOS7 Design Manager interface provided Hank with just the tool he needed. For each cell that required changes, Hank got a list of cells that were using this particular cell, Figure 2. With that list, he could then surgically optimize only the cells with the most impact on power consumption.

Figure 2.

Today’s designs are more complex than ever, and the pressure on engineers to deliver increasingly sophisticated solutions on time and on budget is extraordinary. Leveraging IP and streamlining the design management process is crucial to success in today’s complex, pressure-cooker design environment. One misstep, one design revision, one or maybe two weeks’ schedule slip can mean the difference between success or failure of a design project.

The solution here was very simple: just use the tools on hand properly to make the best judgment call. Thankfully for Hank, he did, and quite a few of his company’s products that used his PLL were designed into toys this past season!