Power Optimization: What’s Next?

Concerns about the power consumed by semiconductors has been on the rise for the past couple of decades, but what can we expect to see coming in terms of analysis and automation from EDA companies, and is the industry ready to make the investment? Ever since Dennard scaling stopped providing automatic power gains by going to a smaller geometry, circa 2006, semiconductors have been increasing... » read more

Executive Insight: Sanjiv Kaul

Sanjiv Kaul, president and CEO of [getentity id="22016" e_name="Calypto"], sat down with Semiconductor Engineering to talk about dynamic power concerns in finFETs, where software fits in, and why high-level synthesis is now a competitive requirement at advanced nodes. What follows are excerpts of that conversation. SE: What's the biggest problem the semiconductor industry is facing right no... » read more

Does EDA Consider RTL Power Optimization As Job Done?

The “Power Buzz” leading into this year’s Design Automation Conference was around System Level Power Architecture and Optimization—some would say the natural progression of EDA towards the next big customer design challenge. This does beg the question of whether EDA considers RTL Power Optimization a mature solution. All products or solutions progress through various stages of maturity,... » read more

Door Busters In Low Power Optimization

The holiday season is upon us, notably a shortened gift buying season at that, which for some only adds to the anxiety felt at this time of year. Many shoppers are out there searching for a door buster deal on that “hot item,” but choices must be made on where to allocate one’s time. Should one stop with the door buster deals or take the time to look further for more practical or traditio... » read more