tag: secure enclave

Side-Channel Attacks Via Cache On the RISC-V Processor Configuration
By Technical Paper Link - 29 Jan, 2023 - Comments: 0

A technical paper titled "A cross-process Spectre attack via cache on RISC-V processor with trusted execution environment" was published by researchers at University of Electro-Communication, Academy of Cryptography Techniques, Technology Research Association of Secure IoT Edge Application based on RISC-V Open Architecture (TRASIO), and AIST. "This work proposed a cross-process exploitation ... » read more

HW-Enabled Security Techniques To Improve Platform Security And Data Protection For Cloud Data Centers And Edge Computing (NIST)
By Technical Paper Link - 06 Dec, 2022 - Comments: 0

A technical paper titled "Hardware-Enabled Security: Enabling a Layered Approach to Platform Security for Cloud and Edge Computing Use Cases" was published by NIST, Intel, AMD, Arm, IBM, Cisco and Scarfone Cybersecurity. Abstract: "In today’s cloud data centers and edge computing, attack surfaces have shifted and, in some cases, significantly increased. At the same time, hacking has becom... » read more

Performance Implications for Multi-Core RISC-V Systems with Dedicated Security Hardware
By Technical Paper Link - 18 Apr, 2022 - Comments: 0

Abstract "The RISC-V instruction set architecture (ISA) is a promising open-source architecture supporting the Open Era of Computing. As RISC-V matures, consumers, industry leaders, and nation states are looking at the potential benefits RISC-V offers –especially for secure systems which may require privileged architecture implementations, physical memory protection (PMP), or trusted executi... » read more

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