Sidestepping Lithography In Chip Manufacturing


Rising lithography costs, shrinking feature sizes, and the need for an alternative to copper are collectively spurring new interest in area-selective deposition. An extension of atomic layer deposition, ASD seeks to build circuit features from the bottom up, without relying on lithography. Lithography will remain a critical tool for the foreseeable future. But it has long been the most expen... » read more

Extending Copper Interconnects To 2nm


Transistor scaling is reaching a tipping point at 3nm, where nanosheet FETs will likely replace finFETs to meet performance, power, area, and cost (PPAC) goals. A significant architectural change is similarly being evaluated for copper interconnects at 2nm, a move that would reconfigure the way power is delivered to transistors. This approach relies on so-called buried power rails (BPRs) and... » read more

Pathfinding Beyond 10nm


After higher aspect-ratio finFETs and higher mobility SiGe and III-V materials, the industry will move to lateral nanowires and then to vertical nanowire transistors, and to new tunnel junction FETs or spin wave architectures ─ or to various combinations of these technologies for different applications, reported An Steegan, Imec senior vice president of process technology, during SEMICON West... » read more