Week In Review: Manufacturing, Test

By Mark LaPedus - 20 Nov, 2020 - Comments: 0

Fab tools PDF Solutions has entered into a definitive agreement to acquire Cimetrix. Under the terms, PDF will pay a cash amount of $35.0 million, net of cash on Cimetrix’s balance sheet as of closing, and subject to other closing adjustments. With the move, PDF will expand into new markets. Cimetrix is a provider of equipment connectivity products for smart manufacturing and Industry 4.0... » read more

What Makes A Chip Tamper-Proof?

By Bryon Moyer - 04 Jun, 2020 - Comments: 5

The cyber world is the next major battlefield, and attackers are busily looking for ways to disrupt critical infrastructure. There is widespread proof this is happening. “Twenty-six percent of the U.S. power grid was found to be hosting Trojans," said Haydn Povey, IAR Systems' general manager of embedded security solutions. "In a cyber-warfare situation, that's the first thing that would b... » read more

Manufacturing Bits: Oct. 22

By Mark LaPedus - 22 Oct, 2019 - Comments: 0

3.5D chip packaging In a recent paper, PacTech has described a vertical laser assisted bonding process for use in developing advanced 3.5D chip packages. Laser assisted bonding (LAB) is an interconnection technology used in IC packaging. It uses a laser as a thermal energy, which in turn connects a die bump and a substrate pad, according to Amkor, which is the original developer of LAB tech... » read more

Manufacturing Bits: Feb. 9

By Mark LaPedus - 09 Feb, 2016 - Comments: 1

3D chip consortium The 3D integration consortium of IRT Nanoelec has a new member--EV Group. Based in Grenoble, France, IRT Nanoelec is an R&D center headed by CEA-Leti. Formed in 2012, the 3D integration consortium is one of IRT’s core programs. EV Group joins Leti, Mentor Graphics, SET and STMicroelectronics as members of the 3D consortium. The program is developing a 3D integration ... » read more

Power/Performance Bits: Feb. 2

By Jesse Allen - 02 Feb, 2016 - Comments: 0

Single electron transistors A group coordinated by the Helmholtz-Zentrum Dresden-Rossendorf (HZDR) is setting out on a four year program to develop single electron transistors fully compatible with CMOS technology and capable of room temperature operation. The single electron transistor (SET) switches electricity by means of a single electron. The SET is based on a quantum dot (consisting... » read more

Manufacturing Bits: Jan. 19

By Mark LaPedus - 19 Jan, 2016 - Comments: 0

Bubble-pen lithography The University of Texas at Austin has developed a new nano-patterning technology--bubble-pen lithography. Researchers have devised a bubble-pen that enables optically-controlled microbubbles. The bubbles are used to pattern structures onto a surface at tiny dimensions. Bubble-pen lithography could be used in microelectronics, nanophotonics, and nanomedicine. In si... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer