Manufacturing Bits: Oct. 22

3.5D chip packaging; 3D consortium; hopfions.


3.5D chip packaging
In a recent paper, PacTech has described a vertical laser assisted bonding process for use in developing advanced 3.5D chip packages.

Laser assisted bonding (LAB) is an interconnection technology used in IC packaging. It uses a laser as a thermal energy, which in turn connects a die bump and a substrate pad, according to Amkor, which is the original developer of LAB technology.

LAB is more reliable than the traditional mass reflow process in chip packaging, according to PacTech and others. LAB is faster and creates less stress than thermal compression bonding (TCB). Used in 2.5D/3D and other package types, a TCB bonder utilizes force and heat to connect bumps in packages.

Today, LAB is used in select, if not niche, applications. “It is in mass production,” according to Matthias Fettke from PacTech, a supplier of IC packaging equipment. “For example, the LAB process is used for cantilever bonding of fine-pitch probe-cards (pitch <60µm), bonding of CT sensor elements in a vertical configuration or for placing and removal of flip chips on the wafer level.”

PacTech has taken LAB a step further. “This new concept allows for the vertical bonding of chips/semiconductors to the sides of a chip stack,” said Andrej Kolbasow from PacTech, in a paper at the recent 2019 IEEE 69th Electronic Components and Technology Conference (ECTC). “The vertically bonded parts can be used to contact the individual layers, which eliminates the necessity for through silicon vias (TSVs).”

Still in R&D, vertical LAB is different than today’s flip-chip bonding or TCB. Typically, in advanced packaging, each side of a die has copper microbumps or pillars. The die bumps/pillars are joined or bonded together using a wafer bonding process in one form or another.

In vertical LAB, though, dies or wafers are stacked. It appears that a dielectric material is deposited between the dies. “The prerequisite for the vertical connection of a functional group to a chip stack or chip package is the presence of lateral contact surfaces,” Kolbasow said in the paper. “Ideally, all of the otherwise on-surface contacts of a microchip may be routed to the side surface.”

Then, two separate substrates with solder bumps are formed. The substrates also have internal copper routing layers. “Prior to the bonding process, the chip had been prepared with solder depots of 80μm size via solder jetting,” Kolbasow said.

In some respects, the substrates perform the same function of a traditional interposer. The big difference is that the substrates are oriented in the vertical direction, not laterally.

In a LAB tool, one substrate is placed in a vertical fashion and bonded on one side of the chip stack. Each bump on the substrate is connected to each chip.

The other substrate is bonded on the other side of the chip stack. Using LAB, the laser hits the chip’s surface at an incident angle of 45°, according to the paper.

“It allows for vertical chip bonding, a technique, with which a microelectronic component can be vertically bonded to the side of an existing chip stack. All four sides of a chip stack can be contacted to generate a 3.5D package,” Kolbasow said. “In the future, ‘3.5D’ stacking will make it possible to contact the individual layers in a chip stack via vertically bonded components and greatly reduce, if not eliminate the need for TSVs.”

3D consortium
Prophesee, a developer of neuromorphic machine vision systems, has joined IRT Nanoelec’s 3D Integration Program.

Headed by CEA-Leti, Nanoelec Research Technological Institute (IRT) conducts R&D in various fields, including 3D integration.

The purpose of IRT Nanoelec’s 3D Integration Program is to develop a 3D integration lab and other technologies. The group is also developing hybrid wafer-to-wafer bonding with fine interconnect pitches for 3D technologies. The group has developed a 3D stacked imager with a 1.44µm pitch.

Hybrid bonding enables a vendor to stack and connect devices directly using fine-pitch copper connections, eliminating the need for bumps and pillars. It paves the way towards more advanced forms of 2.5D, 3D-ICs and 3D DRAMs.

IRT Nanoelec’s 3D integration group includes STMicroelectronics, Mentor, a Siemens business, EV Group, SET and CEA-Leti.

Johannes Gutenberg-University Mainz, Forschungszentrum Jülich and Radboud University Nijmegen have been awarded a grant to explore nanoscale 3D magnetic structures.

This effort, called the “3D MAGiC” project, is funded by the European Research Council (ERC). The ERC recently awarded synergy grants to 37 projects across Europe.

3D MAGiC is one of those projects. 3D magnetic structures are theoretical particles, but little is known about them. If they are proven, these particles are relevant in various fields, such as astronomy and sub-atomic physics. In theory, 3D magnetic structures could be used as information carriers in spin-wave devices.

In the project, researchers will study so-called magnetic solitions, which are tiny magnetic whirls. These nanoscale particles are present in solid-state systems. In addition, researchers also want to investigate various other particles, namely hopfions.

“The first magnetic vortices that were detected can be regarded as two-dimensional objects. We are now at a threshold where it will be possible to experimentally study three-dimensional vortex-like structures. One of our goals is to extend our methods of electron holography for this purpose,” said Rafal Dunin-Borkowski, a professor at Forschungszentrum Jülich.

“(Hopfions are particles that) can be imagined as twisted or knotted shoelaces. The more loops they contain, the higher the Hopf number,” said Stefan Blügel from Forschungszentrum Jülich.

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