Chip Industry Technical Paper Roundup: Feb. 24


New technical papers recently added to Semiconductor Engineering’s library: [table id=525 /] Find more semiconductor research papers here. » read more

Chip Industry Technical Paper Roundup: Jan 6


New technical papers recently added to Semiconductor Engineering’s library: [table id=510 /] Find more semiconductor research papers here. » read more

MoS2 Memristors With Fast Switching Speed and Low Power Consumption (AMO, RWTH Aachen et al.)


A new technical paper titled "Intermediate Resistive State in Wafer-Scale Vertical MoS2 Memristors Through Lateral Silver Filament Growth for Artificial Synapse Applications" was published by researchers at AMO GmbH, RWTH Aachen, Forschungszentrum Jülich, Peter Grünberg Institute, Eindhoven University of Technology et al. Abstract "Memristors based on 2D materials have garnered signifi... » read more

Chip Industry Week in Review


SEMICON West was held in Phoenix this week, with presentations covering heterogeneous integration, AI, quantum, supply chain resilience, and more. Amid the buzz of the conference, some key manufacturing and test announcements were made this week: The strategic importance of the Phoenix area hub was highlighted. Amkor Technology broke ground this week on its advanced packaging and test camp... » read more

Chip Industry Technical Paper Roundup: Sept 23


New technical papers recently added to Semiconductor Engineering’s library: [table id=478 /] Find more semiconductor research papers here. » read more

Analog IMC Attention Mechanism For Fast And Energy-Efficient LLMs (FZJ, RWTH Aachen)


A new technical paper titled "Analog in-memory computing attention mechanism for fast and energy-efficient large language models" was published by researchers at Forschungszentrum Jülich and RWTH Aachen. Abstract "Transformer networks, driven by self-attention, are central to large language models. In generative transformers, self-attention uses cache memory to store token projec... » read more

Research Bits: August 19


Co-packaged optics Researchers from the Massachusetts Institute of Technology (MIT) and Bridgewater State University developed a new way to co-package photonic and electronic chips that uses existing automated pick-and-place assembly equipment in traditional fabs along with a less-expensive passive alignment process. “We’ve developed a packaging design [for integrating photonics with el... » read more

Chip Industry Technical Paper Roundup: Apr. 22


New technical papers recently added to Semiconductor Engineering’s library: [table id=421 /] Find more semiconductor research papers here. » read more

Single Transistor Memory Cell C2RAM Based On FDSOI For Quantum And Neuromorphic


A new technical paper titled "An Energy Efficient Memory Cell for Quantum and Neuromorphic Computing at Low Temperatures" was published by researchers at Forschungszentrum Jülich, RWTH Aachen University and SOITEC. Abstract: "Efficient computing in cryogenic environments, including classical von Neumann, quantum, and neuromorphic systems, is poised to transform big data processing. The que... » read more

Research Bits: Mar. 25


2D materials in 3D transistors Researchers at the University of California Santa Barbara investigated 3D gate-all-around (GAA) transistors made using 2D semiconductors. They considered three different approaches to channel stacking: nano-sheet FETs, nano-fork FETs, and nano-plate FETs. The nano-plate FET architecture, which exploits lateral stacking of 2D layers, was found to maximize the g... » read more

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