Using Formal Verification To Evaluate The HW Reliability Of A RISC-V Ibex Core In The Presence Of Soft Errors


A technical paper titled “Using Formal Verification to Evaluate Single Event Upsets in a RISC-V Core” was published by researchers at University of Southampton. Abstract: "Reliability has been a major concern in embedded systems. Higher transistor density and lower voltage supply increase the vulnerability of embedded systems to soft errors. A Single Event Upset (SEU), which is also calle... » read more

Early Cycle Analysis And Verification Of Logical SEU Mitigation


The global appetite for data continues to soar, driving innovation across all industry sectors, including how space-based technology can facilitate a more connected world. Miniaturized satellites configured into constellations offer faster communication and higher bandwidth than lone satellites flying higher in geocentric or high-earth orbits. However, industry analysis suggests that to make... » read more

Mitigating The Effects Of Radiation On Advanced Automotive ICs


The safety considerations in an automotive IC application have similarities to what is seen in other safety critical industries, such as the avionics, space, and industrial sectors. ISO 26262 is the state-of-the-art safety standard guiding the safety activities and work products required for electronics deployed in an automotive system. ISO 26262 requires that a design be protected from the eff... » read more

What Makes A Chip Tamper-Proof?


The cyber world is the next major battlefield, and attackers are busily looking for ways to disrupt critical infrastructure. There is widespread proof this is happening. “Twenty-six percent of the U.S. power grid was found to be hosting Trojans," said Haydn Povey, IAR Systems' general manager of embedded security solutions. "In a cyber-warfare situation, that's the first thing that would b... » read more