Chip Industry Technical Paper Roundup: June 8


New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations DTCO of NOR-Type IGZO FeFETs for 3D Heterogeneous AI Memories: A Read-Centric Perspective 🔗 imec, KU Leuven ZK-Flex: A Flexible and Scalable Framework for Accelerating Zero-Knowledge Proofs 🔗 KAIST Thermal- and Aging-Aware Rowhamme... » read more

Scaling Nanoribbon Transistors with Monolayer TMDs (Stanford, Chalmers, Horiba, SLAC)


Researchers from Stanford University, Chalmers University of Technology, HORIBA Scientific, and SLAC National Accelerator Laboratory have published “Scaling nanoribbon transistors with monolayer transition metal dichalcogenides”. Abstract “Nanoscale transistors demand aggressive scaling of all channel dimensions—length, width and thickness. Two-dimensional semiconductors (2DS... » read more

Chip Industry Technical Paper Roundup: Jan 6


New technical papers recently added to Semiconductor Engineering’s library: [table id=510 /] Find more semiconductor research papers here. » read more

Channel-Last GAA NS Oxide FET (Stanford, TSMC, ETH Zurich et al.)


A new technical paper titled "Channel-last gate-all-around nanosheet oxide semiconductor transistors" was published by researchers at Stanford University, TSMC, ETH Zurich, SLAC National Accelerator Laboratory, and Polish Academy of Sciences. Abstract "As we move beyond the era of transistor miniaturization, back-end-of-line-compatible transistors that can be stacked monolithically in the t... » read more

Chip Industry Technical Paper Roundup: Nov. 18


New technical papers recently added to Semiconductor Engineering’s library: [table id=492 /] Find more semiconductor research papers here. » read more

3D Imaging Buried Interfaces In Twisted Oxide Moirés (Cornell, SLAC, Stanford et al.)


A new technical paper titled "Mind the Gap -- Imaging Buried Interfaces in Twisted Oxide Moirés" was published by researchers at Cornell University, SLAC National Accelerator Laboratory, Stanford University, USC, North Carolina State University, University of Chicago, Institute for Basic Science and POSTECH. Abstract "The ability to tune electronic structure in twisted stacks of layered, t... » read more

Chip Industry Technical Paper Roundup: Oct. 7


New technical papers recently added to Semiconductor Engineering’s library: [table id=480 /] Find more semiconductor research papers here » read more

Scaling Nanoribbon Transistors Based on Monolayer 2D Semioconductors (Stanford, HORIBA, SLAC)


A new technical paper titled "Scaling High-Performance Nanoribbon Transistors with Monolayer Transition Metal Dichalcogenides" was published by researchers at Stanford University, HORIBA Scientific, and SLAC National Accelerator Laboratory. Abstract "Nanoscale transistors require aggressive reduction of all channel dimensions: length, width, and thickness. While monolayer two-dimensional se... » read more

Chip Industry Week In Review


The U.S. Department of Commerce and Amkor Technology signed a deal to provide up to $400 million in funding, under the CHIPS and Science Act, to build a previously announced end-to-end advanced packaging plant. The combined funding is expected to total about $2 billion. The new facility will add some 2,000 jobs in Peoria, Arizona. The SK hynix Board approved its Yongin Semiconductor Cluster... » read more

Chip Industry Week In Review


By Gregory Haley, Jesse Allen, and Liz Allan TSMC told equipment vendors to delay deliveries of the most advanced tools due to uncertain demand, according to Reuters. The news drove down stock prices of all the major equipment providers. On the other hand, TSMC said advanced packaging shortages will constrain AI chip shipments for the next 18 months, according to NikkeiAsia. The United St... » read more

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