tag: SoC architecture

Partitioning In The Chiplet Era
By Ann Mutschler - 03 Oct, 2024 - Comments: 0

The widespread adoption of chiplets in domain-specific applications is creating a partitioning challenge that is much more complex than anything chip design teams have dealt with in previous designs. Nearly all the major systems companies, packaging houses, IDMs, and foundries have focused on chiplets as the best path forward to improve performance and reduce power. Signal paths can be short... » read more

Brain-Inspired Computing
By Ann Mutschler - 18 May, 2015 - Comments: 0

Approaching power/performance tradeoffs from an architectural perspective is essential given the complexities of today’s SoCs. And beyond some traditional techniques that I discussed in a recent article, Bernard Murphy, CTO at Atrenta mentioned that there is currently a lot of buzz about using non-Von Neumann architectures — especially for recognition functions (voice, image and text). ... » read more

The Art Of LP Analog
By Ann Mutschler - 12 Feb, 2015 - Comments: 0

The best way to reduce power in analog chips is to make architectural changes or adopt a new architecture for the individual block. However, there are also some design techniques used to reduce power in analog circuitry. Unlike digital circuitry, which allows an engineer to leverage a low power library and optimize through a constraints file with the EDA software to reduce power, the same do... » read more

Architecting For Efficiency
By Ann Mutschler - 10 Apr, 2014 - Comments: 0

By definition, to be efficient is to perform or function in the best possible manner with the least waste of time and effort; having and using requisite knowledge, skill, and industry. As this relates to SoC design today, achieving the highest level of efficiency is a challenge with many dimensions. Efficiency comes in multiple ways. “One dimension would be power consumption,” said Oz Le... » read more

The Power Game
By Ann Mutschler - 11 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler Semiconductor engineering teams always have focused on stepping up performance in new designs, but in the mobile, GPU and tablet markets they’re finding that maintaining the balance between higher performance and the same or lower power is increasingly onerous. The reason: Extreme gaming applications can create scenario files that cause dynamic power consumpt... » read more

A Balancing Act
By Ann Mutschler - 14 Mar, 2013 - Comments: 0

By Ann Steffora Mutschler If you stay current on data center trends, you are well-versed on the fact that Intel reported last June energy proportionality has effectively doubled server efficiency and workload scaling beyond what Moore’s Law predicted. What does this have to do with power management of SoCs? Cary Chin, director of marketing for low-power solutions at Synopsys, said tha... » read more

SoC Architects Face Big Challenges
By Ed Sperling - 31 Jan, 2013 - Comments: 0

By Ann Steffora Mutschler While the geometries of advanced node processes such as 28nm and below may not greatly impact SoC architectures, the complexity enabled by the leading edge brings intense challenges all the same. With the ability to put more transistors onto a chip come new possibilities such as the increasing use of multi-core architectures and lots of integrated hardware en... » read more

What’s Ahead For System-Level Design
By Ed Sperling - 19 Dec, 2012 - Comments: 0

By Ann Steffora Mutschler Architecting an SoC today is incredibly difficult. When you add in the number of available transistors, the manufacturing effects of smaller nodes, IP and software that must be integrated, among other things, the challenges just keep mounting. Depending on what market segment the SoC will be designed into has a huge impact, as well. “It is impossible to ove... » read more

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