EDA On Cloud Presents Unique Challenges

By Ann Mutschler - 31 Mar, 2022 - Comments: 0

Discussions about cloud-based EDA tools are heating up for both hardware and software engineering projects, opening the door to vast compute resources that can be scaled up and down as needed. Still, not everyone is on board with this shift, and even companies that use the cloud don't necessarily want to use it for every aspect of chip design. But the number of cloud-based EDA tools is growi... » read more

Week in Review – IoT, Security, Autos

By Jeff Dorsch - 04 Oct, 2019 - Comments: 0

Products/Services Cadence Design Systems is working with Adesto Technologies to grow the Expanded Serial Peripheral Interface (xSPI) communication protocol ecosystem, for use in Internet of Things devices. The Cadence Memory Model for xSPI allows customers to ensure optimal use of the octal NOR flash with the host processor in an xSPI system, including support for Adesto’s EcoXiP octal xSPI ... » read more

IaaS vs. SaaS

By Ed Sperling - 24 May, 2012 - Comments: 0

By Ann Steffora Mutschler There has been a lot of confusion about what kind of cloud-based service the EDA industry offers. Here are two different business models. Infrastructure as a service (IaaS) In this most basic cloud service model, cloud providers offer computers – as physical or more often as virtual machines, raw (block) storage, firewalls , load balancers, and networks. IaaS pr... » read more

Slow Start To Software-As-A-Service

By Pallab Chatterjee - 17 Dec, 2009 - Comments: 0

By Pallab Chatterjee Can software as a service (SaaS) really work in the SoC design tools world? While many of the large EDA vendors continue to experiment with it, the future of this model isn’t especially promising. This is contrary to the overall trend among big software makers, which even in the large enterprise applications space are finding success with SaaS and the related cl... » read more

Knowledge Centers
Entities, people and technologies explored

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: software as a service

EDA On Cloud Presents Unique Challenges

Week in Review – IoT, Security, Autos

IaaS vs. SaaS

Slow Start To Software-As-A-Service

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