tag: Sonics

Running Out Of Energy?
By Ann Mutschler - 16 Mar, 2016 - Comments: 1

The anticipated and growing energy requirements for future computing needs will hit a wall in the next 24 years if the current trajectory is correct. At that point, the world will not produce enough energy for all of the devices that are expected to be drawing power. A report issued by the Semiconductor Industry Association and Semiconductor Research Corp., bases its conclusions on system-le... » read more

New Memory Approaches And Issues
By Ed Sperling - 14 Mar, 2016 - Comments: 1

New memory types and approaches are being developed and tested as DRAM and Moore's Law both run out of steam, adding greatly to the confusion of what comes next and how that will affect chip designs. What fits where in the memory hierarchy is becoming less clear as the semiconductor industry grapples with these changes. New architectures, such as [getkc id="202" kc_name="fan-outs"] and [getk... » read more

IP Risk Sharing
By Brian Bailey - 10 Mar, 2016 - Comments: 0

For most people within the semiconductor industry, managing risk involves making the right product decisions that will enable a company to be profitable, and ensuring the product is successfully produced within the necessary time window. In contrast, for products within high-risk areas such as medical and mil/aero, design often proceeds at a slower pace, using proven technologies and adopting l... » read more

Mixed-Signal Design Powers Ahead
By Ann Mutschler - 10 Mar, 2016 - Comments: 1

Mixed-signal devices are at the heart of many advanced systems today because of the need to interact with the outside world, but designing and verifying these systems is getting harder. There are several reasons for this. First, almost all of these devices now have to be lower power than in the past, and in the analog space it's not as simple as just dialing down part of a block. Second, it ... » read more

How Many Cores? (Part 1)
By Ed Sperling - 10 Mar, 2016 - Comments: 2

The optimal number of processor cores in chip designs is becoming less obvious, in part due to new design and architectural options that make it harder to draw clear comparisons, and in part because just throwing more cores at a problem does not guarantee better performance. This is hardly a new problem, but it does have a sizable list of new permutations and variables—right-sized heteroge... » read more

Powerful New Standard
By Brian Bailey - 02 Mar, 2016 - Comments: 1

In December 2015, the IEEE released the latest version of the 1801 specification, titled the IEEE standard for design and verification of low-power integrated circuits, but most people know it as UPF or the Unified Power Format. The standard provides a way to specify the power intent associated with a design. With it, a designer can define the various power states of the design and the contexts... » read more

IP Requirements Changing
By Brian Bailey - 25 Feb, 2016 - Comments: 0

Twenty years ago the electronics industry became interested in the notion of formalizing re-use through third-party IP. It has turned out to be harder than anyone imagined. In 1996, the Virtual Socket Interface Alliance ([getentity id="22845" comment="VSIA"]) was formed to standardize the development, distribution and licensing of IP. Soon afterward, companies with a couple of people in a ga... » read more

Masters Of Abstraction
By Ann Mutschler - 25 Feb, 2016 - Comments: 0

Good system designers are a unique breed. While it's easy enough to distinguish the traits that define a good one from a weak one, it's much harder to determine who possesses those traits before they are put to the test, or whether or how they can be taught. However, there is definitely a particular perspective that good system designers hold in common. The key is the ability to work with ma... » read more

Getting Formal About Debug
By Brian Bailey - 25 Feb, 2016 - Comments: 0

While much of the design and verification flows have been automated, debug remains the problem child. It has defied automation and presents a management nightmare due to the variability of the process. In recent articles about debug, we examined how much time development teams spend in the debug process and some of the reasons why it is becoming a bigger problem. This includes issues such as ex... » read more

Reaching For ROI
By Ann Mutschler - 17 Feb, 2016 - Comments: 0

The simplest way to assess power and performance ROI of a chip design is to ask if the chip works and whether it meets the design specifications. But chips can be used in very different ways, and a single chip may have a number of operational modes, so that formula isn't so clear anymore. "Preventing failures is the No. 1 priority when it comes to ROI," said Aveek Sarkar, vice president of p... » read more

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