Failure analysis for 2.5D/3D chips
Imec has developed a new failure analysis method to localize interconnection failures in 2.5D/3D stack die with through-silicon vias (TSVs).
This technique is called LICA, which stands for light-induced capacitance alteration. It addresses the reliability issues for 2.5D/3D devices in a non-destructive and cost-effective manner at the wafer level.
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