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Lower Power Chips: What To Watch Out For


Low-power design in advanced nodes and advanced packaging is becoming a multi-faceted, multi-disciplinary challenge, where a long list of issues need to be solved both individually and in the context of other issues. With each new leading-edge process node, and with increasingly dense packaging, the potential for problematic interactions is growing. That, in turn, can lead to poor yield, cos... » read more

The Case For FPGAs In Cars


Field-programmable gate arrays (FPGAs) thrive in rapidly evolving new markets before being replaced by hard-wired ASICs, but in automotive that crossover is likely to happen significantly later than in the past. Historically, FPGAs have held temporary positions until volumes increased enough to cost-reduce the FPGAs out in favor of a hardened version. With automobiles, there are so many chan... » read more

Lots Of Little Knobs For Power


Dynamic power is becoming a much bigger worry at new nodes as more finFETs are packed on a die and wires shrink to the point where resistance and capacitance become first-order effects. Chipmakers began seeing dynamic power density issues with the first generation of [getkc id="185" kc_name="finFETs"]. While the 3D transistor structures reduced leakage current by providing better gate contro... » read more

Managing Dynamic Power


Working with finFETs is a study in contrasts. While leakage is now under control for the first time in several process generations due to the advent of different gate technology, dynamic power density caused by tightly packed transistors and higher clock speeds has become the big issue. “FinFET technology helps with reducing static/leakage power so when your logic is not active, you can sh... » read more

Tech Talk: Power Tools


At 200 million gates, using standard tools for power will add weeks to the semiconductor design process. Vijay Chobisa, product marketing manager at Mentor Graphics, talks with Semiconductor Engineering about where the problems are and how to solve them. [youtube vid=w7yEdtaIb9A] » read more

Dealing With New Bottlenecks


By Ed Sperling While the number of options for improving efficiency and performance in designs continues to increase, the number of challenges in getting chips at advanced process nodes out the door is increasing, too. Thinner wires, routing congestion, more power domains, IP integration and lithography issues are conspiring to make design much more difficult than in the past. So why aren... » read more