Executive Insight: Prakash Narain

By Ed Sperling - 27 May, 2014 - Comments: 0

SE: What’s your biggest concern? Narain: We are a smaller company, and ultimately we compete on the basis of the quality of the solutions we provide to customers. What’s the value proposition? How many X better will our solution be compared to the existing solutions that are in deployed in the market? You make a projection about it in your mind, and you make investments, and until they�... » read more

Billion-Gate Signoff

By Graham Bell - 30 Jan, 2014 - Comments: 0

At last year’s Design and Verification Conference in San Jose, Real Intent had a tutorial session on “Pre-Simulation Verification for RTL Sign-Off.” This was a start of conversation in the industry that we have seen grow through DAC 2013 in Austin, and which is getting louder each day. Verification companies are now talking about crossing the billion-gate threshold and what can be done to... » read more

The Race For Better Verification

By Graham Bell - 21 Nov, 2013 - Comments: 0

SoC verification is gearing up for renewed competition among the big vendors and verification-only companies like Real Intent. They are delivering their next-generation SoC verification suites with a focus on specific areas of concern. Clock-domain crossing, X-verification and reset optimization, SDC correctness and consistency, are some of the areas that are receiving dedicated RTL analysis us... » read more

Cracking The Tough Nut Using Formal Methods

By Brian Bailey - 21 Nov, 2013 - Comments: 1

Pranav Ashar, CTO of Real Intent, assured a packed room of researchers and practitioners of formal methods at the recent FMCAD conference: “Static verification is being used in the verification of designs. Every major chip out there is using static methods for sign-off today.” He used an analogy of cracking a nut. “There’s a right way and a wrong way and if you don’t pick the right me... » read more

Shifts In Verification

By Ed Sperling - 25 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler Verifying an SoC requires a holistic view of the system, and engineering teams use a number of tools to reach a high degree of confidence in the coverage. But how and when to use those tools is in flux as engineering teams wrestle with increasing complexity at every level of the design, and a skyrocketing increase in the challenge of verifying it. There are no ... » read more

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tag: static verification

Executive Insight: Prakash Narain

Billion-Gate Signoff

The Race For Better Verification

Cracking The Tough Nut Using Formal Methods

Shifts In Verification

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