Strain Engineering in 2D FETs (UCSB)


A new technical paper titled "Strain engineering in 2D FETs: Physics, status, and prospects" was published by researchers at UC Santa Barbara. "In this work, we explore the physics and evaluate the merits of strain engineering in two-dimensional van der Waals semiconductor-based FETs (field-effect-transistors) using DFT (density functional theory) to determine the modulation of the channel m... » read more

Models for Both Strained and Unstrained GAA FETs Using Neural Networks


A new technical paper titled "Impact of Strain on Sub-3 nm Gate-all-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach" was published by researchers at Hanyang University and Alsemy Inc. Abstract "Impact of strain of sub-3 nm gate-all-around (GAA) CMOS transistors on the circuit performance is evaluated using a neural compact model. The model was trained using 3D... » read more

Manufacturing Bits: May 29


Utilizing Heat For Energy One of the big problems in electronics in general, and semiconductors particular, is heat. And it's not just about leakage current anymore. Heat is a problem at every level, from circuit design to the materials being used inside the chips, as well as warpage between die caused by heat after they are packaged together. Heat can prematurely age chips as well as destroy ... » read more