Week In Review: Manufacturing, Design, Test

By Mark LaPedus - 17 Jan, 2014 - Comments: 0

A new study from Crucial.com reveals that on some days, 64% of U.S. parents spend more time with their computers than with family or close friends. TSMC posted mixed results in the fourth quarter of 2013. It also announced flat CapEx targets for 2014. TSMC also addressed Intel’s recent comments about TSMC’s finFET plans. Morris Chang, chairman of TSMC, said Intel’s comments are mislead... » read more

Blog Review: Oct. 3

By Ed Sperling - 03 Oct, 2013 - Comments: 0

Cadence’s Brian Fuller rolls out a twice-monthly TV program called “Unhinged,” which he bills as a cross between The Daily Show, Letterman and ESPN. The intro is a classic. Who needs coffee? Synopsys’ Karen Bartleson interviews Bob Metcalfe, co-inventor of Ethernet, creator of Metcalfe’s Law—which has withstood the test of time quite well—on why Ethernet still really important.... » read more

Foundry Talk

By Ed Sperling - 07 Jul, 2013 - Comments: 0

GlobalFoundries CEO Ajit Manocha sounds off on Foundry 2.0, 450mm wafers, lithography challenges, stacked die, the Internet of Things and the rush to the next process node. [youtube vid=WfjtlZkCi0w] » read more

Scaling The Lowly SRAM

By Mark LaPedus - 05 Jun, 2013 - Comments: 0

By Mark LaPedus Chipmakers face a multitude of challenges at the 20nm logic node and beyond, including the task of cramming more functions on the same chip without compromising on power and performance. There is one major challenge that is often overlooked in the equation—scaling the lowly static RAM (SRAM). In one key application, SRAM is the component used to make on-chip cache memories... » read more

Multicore Madness

By Mark LaPedus - 21 Feb, 2013 - Comments: 0

By Mark LaPedus Smartphones and tablets are migrating towards new and faster application processors, basebands, graphics chips and memories. In the cell-phone chipset area alone, there are a multitude of options and design considerations. Some devices combine the application processor and modem on the same chip. Some are separate devices. In addition, the architectures range from single- to... » read more

To Shrink Or Not To Shrink…And How Much?

By Ed Sperling - 29 Nov, 2012 - Comments: 0

By Ann Steffora Mutschler The 28nm semiconductor manufacturing node is in full swing with 20nm process development ramping quickly. As such, the industry has been looking ahead to the next node shrink to achieve the power, performance and cost advantages that a node shrink promises. However, as we are well aware by now, traditional CMOS planar technology is not scaling as it did in previous ge... » read more

Fabless-Foundry Model Under Stress

By Ed Sperling - 26 Jun, 2012 - Comments: 0

By Mark LaPedus The semiconductor roadmap was once a smooth and straightforward path, but chipmakers face a bumpy and challenging ride as they migrate to the 20nm node and beyond. Among the challenges seen on the horizon are the advent of 3D stacking, 450mm fabs, new transistor architectures, multi-patterning, and the questionable availability of extreme ultraviolet (EUV) lithography. ... » read more

5 Ways To Cut Power

By Ed Sperling - 16 Jun, 2011 - Comments: 0

By Ed Sperling Low energy consumption with minimal leakage has emerged as the most competitive element in an IC design, regardless of whether it involves a plug, a battery, or whether it’s powered by a gasoline engine. While components on an SoC aren’t always power-aware, they’ll have to be in the future as consumers focus first on energy efficiency. With rising fuel costs, a concern ... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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