tag: Synapse Design

Week In Review: Design, Low Power
By Jesse Allen - 02 Jul, 2021 - Comments: 0

Tools Imperas and Valtrix inked a multi-year distribution and support agreement that makes Imperas simulation technology and RISC-V reference models available pre-integrated within Valtrix STING for RISC-V processor verification. The combined solution covers the full RISC-V specification for user, privilege, and debug modes, including all ratified standard extensions, and the near ratified (st... » read more

The Week In Review: Design
By Jesse Allen - 08 Dec, 2017 - Comments: 0

M&A Design services firm Synapse Design acquired the assets of ACEIC Design Technologies, including the engineering team and verification IP. ACEIC, which was based in Bangalore, primarily focused on verification services for wireless 802.11ac MAC IP. This is only the latest expansion move from Synapse. Earlier this year, the company acquired the services companies Tech Vulcan in San Diego... » read more

The Week In Review: Design
By Jesse Allen - 14 Apr, 2017 - Comments: 0

M&A Synapse Design acquired Asilicon, a design services firm based in Ranchi Jharkhand, India. Through the acquisition, Synapse Design adds a second design center in India and gains an additional 80 engineers. "The focus of the Ranchi office will be to provide lower-cost offshore design center services for our customer's designs targeting 7- and 10-nm process technology," said Satish Bag... » read more

Designing SoC Power Networks
By Brian Bailey - 11 Aug, 2016 - Comments: 0

Designing a power network for a complex SoC is becoming critical for the success of the product, but most chips are still using old techniques that are ill-suited to the latest fabrication technologies, resulting in an expensive, overdesigned product. Not only is the power network as designed too large, but this has several knock-on effects that impact area, timing and power. In the first pa... » read more

SoC Power Grid Challenges
By Brian Bailey - 14 Jul, 2016 - Comments: 7

The consumption of power and dissipation of heat within large SoCs has received a lot of attention recently, but that is only part of the issue. Power also has to be reliably delivered onto and around the system. This is becoming increasingly difficult, and new nodes are adding to the list of challenges. "If we were building chips where there was only a single Vdd and Vss then it is not that... » read more

Why IP Subsystems And Why Now?
By Rich Wawrzyniak - 23 Jun, 2016 - Comments: 0

At the recently concluded DAC 2016 conference in Austin, Texas, I had the opportunity to participate in a tutorial on IP Subsystems on Wednesday the 8th. Also participating were Marco Brambilla, Director of Engineering at Synapse Design and Drew Wingard, CTO at Sonics. The reality today is that device complexity in many applications has risen to levels that require increasing amounts of disc... » read more

Near-Threshold Computing
By Brian Bailey - 16 Jun, 2016 - Comments: 2

The emergence of the Internet of Things (IoT) has brought a lot of attention to the need for extremely low-power design, and this in turn has increased the pressure for voltage reduction. In the past, each new process node shrunk the feature size and lowered the nominal operating voltage. This resulted in a drop in power consumption. However, the situation changed at about 90nm in two ways. ... » read more

Asynchronous’ Impact On Tools
By Ann Mutschler - 25 Jun, 2015 - Comments: 0

In the right situation, using asynchronous logic makes a lot of sense—especially for security and IoT. But moving into the asynchronous design involves making tradeoffs, figuring out how the technical requirements of an application will impact the design, and understanding the limits of EDA tools in this area. “It's going to be halfway between digital and analog support,” said Bernard ... » read more

Memory Design At 16/14nm
By Brian Bailey - 28 May, 2015 - Comments: 0

As we get older the memory may start to fade, but that is not a viable option if we are talking about embedded memory. Chips contain increasing amounts of memory, and for many designs memory consumes more than half of the total chip area. “At 28nm we saw a few people with greater than 400Mbits of memory on chip,” says Prasad Saggurti, product marketing manager for Embedded Memory IP at [... » read more

How Hard Is FD-SOI Design?
By Ann Mutschler - 21 May, 2015 - Comments: 0

Fully-depleted silicon-on-insulator ([getkc id="220" kc_name="FD-SOI"]) manufacturing technology reached of point of readiness for mass production at the end of March. Along with that, it’s now clear that while there are some impacts on the design flow, those impacts are not game changers. For one thing, the tools required are the same ones currently used for 28nm planar bulk CMOS. The onl... » read more

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