Experts At The Table: SoC Prototyping

By Ed Sperling - 27 Jun, 2013 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss SoC prototyping with Hillel Miller, pre-silicon verification/emulation manager at Freescale Semiconductor; Frank Schirrmeister, group director, product marketing, for the system development suite at Cadence; and Mick Posner, director of product marketing at Synopsys. What follows are excerpts of that conversation. SLD: How... » read more

The Ubiquitous GPU

By Ann Mutschler - 27 Jun, 2013 - Comments: 0

By Ann Steffora Mutschler No matter the application area, GPUs are likely playing a role like never before—even to accelerate EDA software algorithms. It’s no wonder given the ability of GPUs to handle parallel processing much more effectively than CPUs. And when coexisting in a heterogeneous system, GPUs allow the design team to maximize efficiency and performance by allocating tasks... » read more

Garbage Or Treasure?

By Jon McDonald - 27 Jun, 2013 - Comments: 0

By Jon McDonald “Garbage in, garbage out” is a very appropriate axiom to keep in mind as you consider what kind of system-level modeling to invest in. Unfortunately this can be complicated by considering another piece of wisdom that often applies as well: “One mans trash is another’s treasure.” What might be an inappropriate abstraction for one type of analysis may be very accepta... » read more

Watching And Waiting For DFP

By Ann Mutschler - 13 Jun, 2013 - Comments: 0

By Ann Steffora Mutschler Although the semiconductor industry has been talking about the need to optimize SoC designs for power for many years, it is safe to say it’s still in the very early stages of the 'Design for Power' approach. That’s not to say that methodologies and tools are not in place. There are actually a number of options available, depending on the level of abstractio... » read more

Formal Verification Comes Of Age

By Ed Sperling - 30 May, 2013 - Comments: 0

By Ann Steffora Mutschler Formal verification technology, also known as formal property checking, has been in existence since the early 1990s. Still, it’s only in the past five years that it has made big strides in the last five years in terms of the capacity of the technology to handle bigger pieces of a design, leveraging advancements in computing as well as improvements to the algor... » read more

The Growing Need For Behavioral Modeling

By Ann Mutschler - 30 May, 2013 - Comments: 0

By Ann Steffora Mutschler When it comes to behavioral or functional modeling, there is an inherent notion of function, architecture and interconnect. This approach has long been considered a future requirement, but in complex designs the future part no longer applies. Behavioral modeling is a way of isolating or abstracting out a key part of the architectural description and making sure i... » read more

Pitfalls In Subsystem Reuse

By Ann Mutschler - 30 May, 2013 - Comments: 0

By Ann Steffora Mutschler IP subsystems provide a ‘divide and conquer’ approach to SoC design by combining multiple IP blocks together to perform individual functions such as audio, graphics or video. The advantage of this approach is that these functions can be tested and verified at the unit level then integrated with the top-level SoC. This also facilitates reuse because each of ... » read more

Divide, Abstract And Conquer

By Ed Sperling - 03 May, 2013 - Comments: 0

For years, the motto among design and verification engineers has been to look at the individual pieces of a design because it’s impossible to have a single tool or even an integrated collection of tools that can debug everything. That approach isn’t changing, but the method for getting there is. The driver behind this shift is a familiar one—growing complexity. Even platforms and subsy... » read more

Shifts In Verification

By Ed Sperling - 25 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler Verifying an SoC requires a holistic view of the system, and engineering teams use a number of tools to reach a high degree of confidence in the coverage. But how and when to use those tools is in flux as engineering teams wrestle with increasing complexity at every level of the design, and a skyrocketing increase in the challenge of verifying it. There are no ... » read more

Design Topology Requires Physical Data

By Ann Mutschler - 25 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler To best understand a design topology and make decisions on clock/register gating, vector sets are required for the RTL tools to understand how to gate clocks and registers. However, if certain constraints are set on all enabled signals in RTL they can be re-used for gating clocks and registers downstream where enablers are not available—even without needing a ... » read more

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