Behind The Scenes

By Ed Sperling - 01 Jul, 2010 - Comments: 0

This year’s DAC should be one of the more interesting shows in several years, although not for the usual reasons. As an industry, we are just emerging from one of the worst downturns in decades. It started in December 2007, and various segments of the overall economy will begin picking up at different times, depending upon whether they’re leading indicators or trailing indicators. Netb... » read more

What Went Wrong At Toyota?

By Ed Sperling - 25 Mar, 2010 - Comments: 0

There’s been a lot of speculation about what caused Toyotas in general, and the Prius in particular, to suddenly accelerate. All across the electronics industry, this is big news because of the amount of electronics that now sits inside an automobile. The most advanced cars have complicated networks of processors, memory, logic, and basically everything that’s already built into the most... » read more

Insurance, Doctors And ESL

By Jon McDonald - 25 Mar, 2010 - Comments: 0

By Jon McDonald Return on investment is a subject that comes up frequently when people are thinking about adopting higher-level design approaches. After all, we are talking about adding work—we need to model, design, simulate and analyze the system. All of these tasks take time and cost money. So what are we getting in return? Before we can think about the return, we have to identify wha... » read more

Still Room For Startups?

By Ed Sperling - 25 Feb, 2010 - Comments: 0

Can startups still survive in an increasingly complex, high up-front investment world? System-Level Design posed that question to Mentor Graphics, Synopsys, Oasys and an end user. [youtube vid=3RGvRnDGiTE] » read more

Low-Power And RF Design Heighten Signal-Integrity Concerns

By Various Writers - 28 Jan, 2010 - Comments: 0

By Ellen Konieczny As active devices and interconnect wires shrink and are placed closer together with the march of Moore’s Law, signal integrity is becoming a huge concern. If it is not maintained, a design’s future may be marred by lower yields, unreliable performance, and failure to work efficiently—if at all. For low-power and radio-frequency (RF) designs, which are being prod... » read more

Synthesis: Next Steps In SoC Design

By Ed Sperling - 17 Dec, 2009 - Comments: 0

Five experts sound off to System-Level Design on the state of synthesis and what's needed in the future: Shawn McCloud, product line director for Catapult C Synthesis at Mentor Graphics; Chris Eddington, director of marketing for system-lvel products at Synopsys; Brett Cline, VP of marketing at Forte Design Systems; Andy Biddle, director of business development at Magma and Sanjiv Kaul, executi... » read more

The Bigger Picture

By Ed Sperling - 11 Dec, 2009 - Comments: 0

The pace of change in system-level design is no longer confined just to technology. It now hinges largely on whether enough engineers can make the leap from RTL or synthesis or verification or any other specialty to systems engineer. This is no small feat. It requires re-tooling and learning of modeling and other concepts that until now have been largely at the architectural level. It may ... » read more

Compression Effect

By Ed Sperling - 19 Nov, 2009 - Comments: 0

For all the talk of restricted design and increasing complexity, it seems that what’s really happening is that restrictions are being lifted off one group and placed on another. This happens from time to time in system-level design, usually at an inflection point in the overall system development process or at the start of a new process node. For the past couple decades, much of the crea... » read more

Methodology Shifts Ahead

By Pallab Chatterjee - 19 Nov, 2009 - Comments: 0

By Pallab Chatterjee The high cost of SoC development at advanced process nodes is forcing a significant shift in many of the methodologies used in design. Hierarchical design methods are giving way to IP integration and hierarchical analysis at the architectural and functional design levels. Previously, large blocks were implemented at the top level of the chip and the analysis was pushe... » read more

Experts At The Table: Evolving Standards

By Ed Sperling - 27 Aug, 2009 - Comments: 0

System-Level Design sat down with Keith Barkley, senior engineer in IBM’s systems and technology group; Steven Schulz, president and CEO of Silicon Integration Initiative (Si2); Yatin Trivedi, director of standards and interoperability programs at Synopsys; Ian Mackintosh, chairman of the OCP International Partnership (OCPIP), and Michael Meredith, vice president of technical marketing at For... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: system-level design