Open Standards For Verification?

By Ann Mutschler - 01 Jun, 2016 - Comments: 0

The increasing use of verification data for analyzing and testing complex designs is raising the stakes for more standardized or interoperable database formats. While interoperability between databases in chip design is not a new idea, it has a renewed sense of urgency. It takes more time and money to verify increasingly complex chips, and more of that data needs to be used earlier in the fl... » read more

UVM Register Layer: The Structure

By Henry Chan - 28 Apr, 2016 - Comments: 0

I don’t know about you, but I am looking forward to the day where we won’t even have to go to the doctor’s office for an exam. Instead, we will all have scanners in our homes that will transmit full digital models to our doctors who can then poke, prod, and examine us remotely. This is essentially what the UVM register layer allows and does. The UVM register layer acts similarly by mod... » read more

Why I See C In SCE-MI

By Jacek Majkowski - 24 Mar, 2016 - Comments: 0

The two questions I hear most often while doing presentations about SCE-MI transaction based emulation are, “Can we have coffee break?” and “Why do we need a thin C layer between two SystemVerilog tops”? You a probably reading this during a coffee break, so let’s jump to second question. It refers to this diagram showing how to connect a SystemVerilog testbench (usually UVM) with D... » read more

Verification Facing Unique Inflection Point

By Brian Bailey - 10 Mar, 2016 - Comments: 0

The Design and Verification Conference and Exhibition (DVCon) attracted more than 1,100 people to San Jose last week, just slightly less than last year. While a lot of focus, and most of the glory, goes to design within semiconductor companies, it is verification where most of the advancements are happening and thus the bigger focus for DVCon. The rate of change in verification and the producti... » read more

Techno-Morality Is Our Concern

By Brian Bailey - 25 Feb, 2016 - Comments: 0

A decade or so ago, [getentity id="22035" e_name="Synopsys"] Chairman of the Board and co-CEO [getperson id="11034" comment="Aart de Geus"] gave a bunch of talks about the importance of Techonomics. Fundamentally this was about the merging of technology and business economics. De Geus saw that we were entering a period of connected everything, and that devices increasingly would be driven by in... » read more

Bridging Hardware And Software

By Ann Mutschler - 18 Jan, 2016 - Comments: 1

Methodology and reuse are two fairly standard concepts when it comes to semiconductor design, but they're viewed completely differently by hardware and software teams. It's a given that hardware and software have different goals and opinions about how best to do design. And while all agree that a single methodology can pay dividends in future chips, there is disagreement over who should shap... » read more

A History of (Premature) Optimization

By Neil Johnson - 22 Dec, 2015 - Comments: 0

I saw some material shared from DVCon Europe last month that suggested a competition brewing between shift left and agile in semiconductor development. As someone who’s been following shift left writing and been advocating for agile development, this kind of comparison is more than a little odd to see. It’s a comparison between two as yet amorphous development strategies, neither of which i... » read more

One Flow To Rule Them All

By Brian Bailey - 12 Nov, 2015 - Comments: 0

The new mantra of shift left within EDA is nothing new and first made an appearance more than a decade ago. At that time there was a very large divide between logic synthesis and place and route. As wire delays became more important, timing closure became increasingly difficult with a logic synthesis flow that did not take that into account. The tools subsequently became tied much closer togeth... » read more

HW Vs. SW: Who’s Leading Whom?

By Brian Bailey - 29 Oct, 2015 - Comments: 6

In the past, technologies were developed in the software world that have languished until they were taken up by the hardware community. Then they were refined and polished and became fully integrated into the hardware development and verification flow. Examples are lint and formal. That was followed by attempts to migrate methodologies, such as object-oriented programming, which is the basis fo... » read more

Blog Review: Sept. 9

By Ed Sperling - 09 Sep, 2015 - Comments: 0

Doulos' John Aynsley explains in a guest blog for Aldec why FPGA designers need to know SystemVerilog and UVM. Might be time to increase the coffee budget. Speaking of verification, Cadence's Frank Schirrmeister notes that his company is joining forces with Mentor Graphics and Breker for a contribution to the Accellera Portable Stimulus Working Group. This is potentially a big deal in veri... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: SystemVerilog