Electric Cars Gain Traction, But Challenges Remain

By Mark LaPedus - 22 Apr, 2019 - Comments: 4

Battery-powered electric vehicles are expected to reach a milestone in terms of shipments in 2019, but the technology faces several significant hurdles to gain wider adoption in the market. Limited driving range, high costs, battery issues, and a spotty charging infrastructure are the main challenges for battery electric vehicles (BEVs). In addition, there are issues with various power semic... » read more

3D NAND Metrology Challenges Growing

By Mark LaPedus - 09 Apr, 2019 - Comments: 8

3D NAND vendors face several challenges to scale their devices to the next level, but one manufacturing technology stands out as much more difficult at each turn—metrology. Metrology, the art of measuring and characterizing structures, is used to pinpoint problems and ensure yields for all chip types. In the case of 3D NAND, the metrology tools are becoming more expensive at each iteration... » read more

3D NAND Flash Wars Begin

By Mark LaPedus - 20 Aug, 2018 - Comments: 0

3D NAND suppliers are gearing up for a new battle amid a period of price and competitive pressures, racing each other to the next technology generations. Competition is intensifying as a new player enters the 3D NAND market—China’s Yangtze Memory Technologies Co. (YMTC). Backed by billions of dollars in funding from the Chinese government, YMTC recently introduced its first 3D NAND techn... » read more

Progress And Chaos On Road To Autonomy

By Jeff Dorsch - 03 Jun, 2018 - Comments: 1

Progress in the development of fully autonomous vehicles is incremental and slow, but not for lack of effort. Research and development in self-driving cars is under way all around the globe, from the biggest automotive manufacturers and their Tier 1 suppliers to companies not traditionally involved in the automotive industry. Add to that fleets of startups working on sensor technologies and ... » read more

Nodes Vs. Nodelets

By Mark LaPedus - 22 Jan, 2018 - Comments: 0

Foundries are flooding the market with new nodes and different process options at existing nodes, spreading confusion and creating a variety of challenges for chipmakers. There are full-node processes, such as 10nm and 7nm, with 5nm and 3nm in R&D. But there also is an increasing number of half-nodes or "node-lets" being introduced, including 12nm, 11nm, 8nm, 6nm and 4nm. Node-lets ar... » read more

Wirebond Technology Rolls On

By Mark LaPedus - 08 May, 2017 - Comments: 2

Several years ago, many predicted the demise of an older interconnect packaging technology called wire bonding, prompting the need for more advanced packaging types. Those predictions were wrong. The semiconductor industry today uses several advanced packaging types, but wire bonding has been reinvented over the years and remains the workhorse in packaging. For example, Advanced Semiconducto... » read more

5 Takeaways from IEDM

By Mark LaPedus - 15 Dec, 2016 - Comments: 1

As usual, the recent IEEE International Electron Devices Meeting (IEDM) was a busy week. The event, which took place in San Francisco, featured a plethora of subjects, such as next-generation transistors and memories. The event also included tracks on non-traditional approaches like quantum and neuromorphic computing. And then, there were sessions on power semis and others. In no partic... » read more

The Week In Review: Manufacturing

By Mark LaPedus - 16 Sep, 2016 - Comments: 0

Chipmakers The finFET market is heating up. GlobalFoundries, Intel, Samsung and TSMC are ramping 16nm/14nm finFETs. And 10nm and 7nm finFETs are in the works. The market will shortly have a new competitor—Taiwan’s United Microelectronics Corp. (UMC). Some years ago, UMC licensed finFET technology from IBM. UMC has been a bit quiet about the 14nm finFET technology, but it has made si... » read more

What’s Next For Memory?

By Mark LaPedus - 14 Aug, 2014 - Comments: 4

Apple, Samsung and others are developing the next wave of smartphones and tablets. OEMs want to integrate new memory schemes that provide more bandwidth at lower power. But there are some challenges in the arena that are prompting memory makers to rethink their mobile DRAM roadmaps. The conventional wisdom was that memory makers would ship mobile DRAMs based on the new LPDDR4 interface stand... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.