Wirebond Technology Rolls On

Technology still being used for new applications, years after it was predicted to be phased out.


Several years ago, many predicted the demise of an older interconnect packaging technology called wire bonding, prompting the need for more advanced packaging types.

Those predictions were wrong. The semiconductor industry today uses several advanced packaging types, but wire bonding has been reinvented over the years and remains the workhorse in packaging. For example, Advanced Semiconductor Engineering (ASE), the world’s largest outsourced semiconductor assembly and test (OSAT) vendor, currently has an installed base of nearly 16,000 wire bonders that are churning out several package types.

Developed in the 1950s, a wire bonder resembles a hi-tech sewing machine that stitches one chip to another chip or substrate using tiny wires. Wire bonding mainly has been used for low-cost legacy packages, mid-range packages, memory die stacking and others.

Fig. 1: Ultra fine pitch wire bonding. Source: Kulicke & Soffa.

Now, the wirebond market is heating up amid a surge for traditional applications like automotive, as well as new segments such as . Wirebond also is being used in advanced packaging. “I would say that roughly 75% to 80% of the packages are still wirebonded,” said Jan Vardaman, president of TechSearch International. “Growth is single-digit, but there are still some growing segments. For example, flash memory is wirebond. Some new sensors will use wirebond. Some packages actually have both wirebond and flip-chip inside.”

But wire bonding has its limits. It won’t take over the IC-packaging world, as the technology has some well-known I/O issues. For many high-performance chips, wire bonding runs out of steam and customers will require more advanced package types.

In fact, some traditional wirebond-based applications are migrating to newer package types. But wire bonding is not standing still and the tools continue to advance. “Wirebond continues to grow, especially for copper wire bonding,” said Scott Chen, vice president of engineering at ASE’s Chung Li facility in Taiwan.

All told, the death of wire bonding is greatly exaggerated. “In some silicon nodes, you can’t simply adopt advanced packaging like flip-chip and wafer-level,” said Edward Fontanilla, deputy director for product and technology marketing at STATS ChipPAC. “Sometimes, wirebond still has an advantage in terms of cost and reliability.”

Chip customers have grown accustomed to the capabilities and limitations of wire bonding, but many are now looking at competitive technologies. To help the industry gain an insight where wirebond is heading, Semiconductor Engineering has taken a look at the technology and some key markets, particularly smartphones.

What is wire bonding?
Wirebond is a mature market that is projected to grow a mere 2.4% from 2014 to 2019, analysts said. But wirebond packaging is still a large business, worth about $13 billion to $15 billion per year, analysts said.

Analog and automotive, two of the bigger drivers for wirebond, are each growing at an annual rate of 3.9%. Computing will fall 6.6%, but sensors are up 15.2%, they added.

Meanwhile, wire bonding is one of the major interconnect technologies in packaging. The others include flip-chip, wafer-level packaging (WLP), and through-silicon vias (TSVs).

At the high end, the industry continues to ramp up 2.5D/3D chips using TSVs. Then, at the mid-range to high end, customers use WLP, such as fan-in and fan-out. WLP involves packaging an IC while it’s still on the wafer.

In flip-chip, a sea of tiny bumps or copper pillars are formed on top of a chip. The device is flipped and mounted on a separate die or board. The die or board consists of copper pads. The bumps or pillars land on the copper pads, forming an electrical connection.

Fig. 2: Flip-chip BGA package. Source: UTAC

Wire bonding, the oldest and lowest cost interconnect scheme, is performed using a wire bonder from ASM Pacific, K&S and others. Bonders are used to make various package types—BGA, PDIP, QFN, SOIC, TSSOP and others.

Basically, there are two main types of wire bonders—ball bonding and wedge bonding. “Over 90% of the market uses ball bonding,” ASE’s Chen said. “Wedge bonding is used for discrete products and power devices with heavy wire.”

In a simple wirebond flow, a chip is first attached to a frame or substrate. Then, using a wire bonder, a wire is fed into a capillary from a spool in the system. Heat creates a tiny ball at the end of the wire. Using force, the bonder welds the ball on the bond pad. The system loops the wire and then stitches it. Finally, a molding compound covers the wires.

Fig. 3: TI’s copper wiring bonding process.

Until 2010, the industry mainly used gold wiring in wirebond-based packages. But when gold prices spiked, the industry migrated from gold to copper wiring. Copper is less expensive than gold, enabling chipmakers to reduce their packaging costs.

Copper is harder than gold, though. This, in turn, requires a higher bonding force, which may cause damage to a bond pad. Moreover, copper undergoes oxidation at certain temperatures.

Today, though, some 70% of wirebond-based packages use copper wiring, while the remaining portion is shared by gold or silver wiring. “The cost of silver is higher than copper, but lower than gold,” Chen said. “The majority of silver wire is used for memory packages.”

Gold wiring is still used in many applications. “Some applications are more conservative. They take a longer time to certify, such as automotive,” he said. “They need more time to prove the device can convert to copper wire. But for some devices, they don’t want to make a change at all.”

Regardless, wire bonding is limited. “Wirebond supports low pin count devices. It can support up to 700 to 800 I/Os, but the actual wire count is over 1,000 wires,” he said.

A decade ago, the bond pad pitch for wire bonding was limited from 80 to 100µm. Over time, the wire bonder has improved, enabling a bond pitch from 40 to 37µm.

“The wire bond machines keep improving,” said Adrian Arcedera, senior vice president of MEMS, sensors and wirebond BGA products at Amkor. “What that allows us to do is not only handle smaller wire diameters as the bond pad pitch shrinks, but it also allows us to have better looping control.”

Still, wire bonders are being asked to perform more complex tasks at finer pitches, causing some throughput challenges. “Because (the wire bonders) have improved, the capabilities have improved,” Arcedera said. “But we also keep challenging the machines. We are making the machines do a number of bends or kinks in the loop. Now, we are slowing them back down again.”

All told, customers have options. They can stick with wirebond or look at flip-chip, WLP or TSVs—or do a combination of everything. Still others may move from wirebond to other technologies. “Some customers are migrating from wirebond products to advanced packaging. Some require a tighter reliability,” STATS ChipPAC’s Fontanilla said. “We also have laminate-based wirebond. (Some may) convert to advanced packaging like flip-chip and wafer-level. That’s the threat for wirebond.”

Inside the iPhone 7
Wire bonding is used for several applications, with automotive being the one that typically comes to mind. “In automotive, we use standard packaging with standard equipment and processes,” Fontanilla said. “The only difference between the automotive and commercial markets is in terms of quality and process control. Automotive is tighter in terms of quality, process and reliability.”

Automotive customers are also less willing to make changes. A given socket might use the same chip and package type for years. That’s not always the case, however. “Some customers are looking at a high reliability product like automated driver assistance systems (ADAS). Instead of wirebonding, they might use a wafer level product,” he said.

It’s a different story in smartphones, however. The next wave of smartphones will require new chips housed in smaller and thinner packages.

Fig. 4: Block diagram of iPhone 7. Source-TechInsights

For example, smartphones traditionally have incorporated package-on-package (PoP) technology for the application processor. PoP stacks two separate packages on top of each other, which are connected using a flip-chip process.

In PoP, a memory package is on the top, while an application processor package is on the bottom. A memory package could consist of one or more die. Basically, the memory die are connected to the substrate using wire bonding.

Many smartphone OEMs are sticking with PoP, as the technology is mature and inexpensive. But PoP is running out of steam at thicknesses at around 0.8mm.

Seeking to displace PoP, the industry is working on an advanced packaging technology called high-density fan-out. In fan-out, the interconnects are fanned out, enabling more I/Os.

Apple’s iPhone 7 is the most notable example of high-density fan-out. TSMC is making Apple’s A10 application processor on a foundry basis for Apple. Based on a 16nm finFET process, Apple’s A10 is housed in TSMC’s fan-out technology, dubbed Integrated Fan-Out (InFO). With InFO, the A10 is housed in a package with a thickness from 0.33mm to 0.23mm, according to TechInsights.

InFO is like a PoP package, where the memory package resides on top and the application processor package is on the bottom. In some fan-out configurations, the memory die are stacked and connected to the substrate via wire bonding. Typically, silver wiring is used to connect the memory die stack. Silver wiring is relatively soft, thereby lowering the risk for pad damage.

Fig. 5: PoP vs WLP fan-out. Source: TechSearch

Meanwhile, in the iPhone 7, there are four LPDDR4 SDRAM die. The die are not stacked, but rather they are spread out across the package, keeping the overall package height to a minimum, according to TechInsights.

“Some fan-out WLP uses wirebond and some do not,” said STATS ChipPAC’s Fontanilla. “Sometimes, they have a combination of wirebond and flip-chip inside the package.”

Indeed, PoP and fan-out can use a combination of several interconnect technologies, which is sometimes referred to as “hybrid packaging.” In addition, a system-in-package (SIP) product can also make use of hybrid packaging. “Inside the package, it’s complicated. It will combine wirebond, flip-chip and wafer-level,” ASE’s Chen said.

Generally, though, hybrid packaging adds cost and complexity to the manufacturing equation. On the other hand, hybrid packaging makes sense. For example, in a smartphone, it makes sense to use fan-out for the application processor for performance reasons.

But smartphones also incorporate other devices, such as MEMS, microcontrollers and RF chips. They also consist of passive components. Most of these chips don’t require advanced packages for cost reasons—wirebond is suitable and less expensive.

Fig. 6: Hybrid packaging. Source: Kulicke & Soffa.

Stacking NAND
For the application processor, the DRAM stack is limited to four die. To save cost, it makes sense to migrate to a 3D DRAM technology, such as high-bandwidth memory (HBM). But HBM is too expensive for the smartphone, at least for now.

NAND is a different story. Typically, the smartphone incorporates standalone NAND chips for data storage. A standard iPhone 7 has 128GB of flash memory. Using traditional planar NAND, the phone stacks 16 128-Gbit die, according to TechInsights.

Commenting on NAND stacking in general, Tony Veches, director of compute DRAM product engineering at Micron Technology, said: “NAND stacks are generally limited to 16 high with wirebond technology. With this technology, there is no mechanical limitation to how many die can be stacked. But we do encounter limitations based on signal integrity and power delivery. That will vary based on the specifics of the die and the application.”

There are other challenges. For example, the NAND stack must meet a certain profile requirement. But as you stack more die, the stack height increases.

To keep within the specs, a packaging house may need to reduce the thickness of each die using a challenging process called wafer thinning. “For example, in a 10 die stack, you require only a 50µm wafer thickness. And when you go 16 die, you will require 30µm,” STATS ChipPAC’s Fontanilla said.

Apple may have solved the problem, however. Some high-end iPhone 7 models are using 3D NAND, enabling a thinner eight-die stack of 256-Gbit dies, according to TechInsights.

The 3D NAND stack might be wirebonded on the board. Unlike 2D NAND, which is a planar structure, 3D NAND consists of multiple layers, which, in turn, increases the density.

More chips and sensors, too

Meanwhile, a smartphone also incorporates a slew of other chips, such as audio ICs, FPGAs, LCD controllers, MCUs, MEMS and others.

Many of these chips require low-profile packages at heights less than 0.5mm. “All of these components need to fit underneath the LCD display,” Amkor’s Arcedera said. “They also need to be thinner.”

For this, there are several packaging options on the table—extremely-thin, fine-pitch BGA (XFBGA); QFN; and WLP.

Quad flat no-leads (QFN) is an old but popular package type, as it enables thin and inexpensive form factors. In QFN, a copper frame or leadframe is placed on the die. The leadframe has pads on each of its four sides. Using a wire bonder, wires connect and stitch the die to the pads.

Fig. 7: QFN. Source: Wikipedia

Based on wire bonding, XFBGA is another contender. Unlike QFN, XFBGA packages use laminate substrates, not leadframes. Then, there is a WLP technology called fan-in, where the I/Os are placed over the solder balls, enabling tiny packages.

The problem is that QFN is limited in terms of routing capabilities. Until recently, XFBGA was limited to about 0.45mm heights. “Flip-chip CSP (designs) can overcome these technical issues and provide another effective solution,” said Yeonho Choi, director of laminate products at Amkor, in a white paper. “But it requires a bumping process on the die, which is a major cost addition, especially if the die design does not allow users to enable cheap enough bumping and under-fill methods.”

To solve the problem, Amkor has developed a lower profile XFBGA technology. It has devised a maximum 0.40mm height XFBGA assembly process. Amkor refers to the technology as ChipArray Ball Grid Array (CABGA).

Fig. 8: XFBA. Source: Amkor

Amkor and other OSATs also offer competitive QFN and WLP products. “We are trying to give options to our customers,” Arcedera said. “Traditionally, this thickness is an area where wafer-level CSP resides. (CABGA) allows our customers, who have traditionally developed wirebonded devices, to compete with a wafer-level solution.”

This presents some advantages for IC designers. “They have their design libraries already built for wirebonded products. So, they can reuse those design libraries to create a chip faster and roll it out in the market versus completely re-tooling it for a flip-chip application. Instead of doing that, we’re offering designers the ability to continue on with their wirebond products for a longer period of time,” Arcedera said.

In addition, today’s smartphones incorporate sensors. In fact, Apple’s iPhone 7 incorporates the following sensor types—fingerprint, accelerometer, gyros, proximity, compass and barometer.

Sensors are a big driver for wire bonding, flip-chip and WLP. “Different sensors have different process requirements,” STATS ChipPAC’s Fontanilla said.

OSATs are seeing growth in several sensor areas, especially fingerprint sensors for ID applications. In total, the fingerprint sensor market for smartphones jumped from 23 million units in 2013 to 689 million units in 2016, a 210% growth rate, according to Yole Développement. But amid the slowdown in smartphones, the fingerprint sensor market is projected to grow by 19% from 2016 to 2022, according to Yole.

Sensors require smaller and thinner form factors. “For fingerprint sensors, the challenge is mostly the mold-to-die clearance. Some customers require higher clearance. Some customers require thinner clearance. The thinner clearance is the challenging part, where we need to do some additional steps just to obtain the exact clearance,” Fontanilla said.

For some time, STATS ChipPAC has been ramping up its packaging capacity for sensors. ASE, Amkor and others are also chasing after the market. Clearly, automotive, mobile, sensors and other markets will continue to drive wire bonding, thereby keeping the technology relevant for years to come.

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Dev Gupta says:

but the funny thing is that the overall thickness of the iPhone 7 w/ the thinner inFO is still the same as the 6 w/ FC, guess have to wait for the 8 to see any obvious benefit

James Lee Tucker says:

It’s great that I found your article and learned that wire bonder connects one chip to another chip using tiny wires. The first time I heard the term “wire bond” was from a friend who developed his own semiconductor and is looking for a company who can do a shear test on the wire bond of his semiconductor. Now I understand and relate to what he was saying. Thanks.

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