Blog Review: Oct. 3

By Jesse Allen - 03 Oct, 2018 - Comments: 0

Applied's Buvna Ayyagari-Sangamalli notes that the requirements of AI are challenging the entire design ecosystem, and while new materials are necessary, so is keeping up the current pace of architecture and EDA development. Mentor's Joe Hupcey III digs into how to handle counters effectively with formal by reducing their size or replacing them with abstract models to allow formal engines to... » read more

Week In Review: Manufacturing, Test

By Mark LaPedus - 07 Sep, 2018 - Comments: 0

Packaging Brewer Science has introduced the latest additions to its family of temporary bonding materials. The company also rolled out its new line of thin spin-on packaging materials. The company’s temporary bonding materials are called BrewerBOND. The new products, called the BrewerBOND T1100 and BrewerBOND C1300 series, are combine to create a dual-layer system for temporary bonding a... » read more

The Chiplet Race Begins

By Mark LaPedus - 06 Aug, 2018 - Comments: 1

Momentum is building for the development of advanced packages and systems using so-called chiplets, but the technology faces some challenges in the market. A group led by DARPA, as well as Marvell, zGlue and others are pursuing chiplet technology, which is a different way of integrating multiple dies in a package or system. In fact, the Defense Advanced Research Projects Agency (DARPA), part... » read more

Mixed Outlook For Semi Biz

By Mark LaPedus - 25 Jul, 2018 - Comments: 0

Both the IC and fab equipment industries have been enjoying a boom cycle for some time, but they could be facing speed bumps and possibly turbulence in the second half of this year and into 2019. In the first half of 2018, the industry was fueled by the momentum carried over from 2017. DRAM prices remained relatively high, which contributed to the revenue growth in the overall IC industry. M... » read more

Bridges Vs. Interposers

By Mark LaPedus - 12 Jul, 2018 - Comments: 4

The number of technology options continue to grow for advanced packaging, including new and different ways to incorporate so-called silicon bridges in products. For some time, Intel has offered a silicon bridge technology called Embedded Multi-die Interconnect Bridge (EMIB), which makes use of a tiny piece of silicon with routing layers that connects one chip to another in an IC package. In ... » read more

Advanced Packaging Confusion

By Ed Sperling - 13 Jun, 2018 - Comments: 2

Advanced packaging is exploding in all directions. There are more chipmakers utilizing different packaging options, more options for the packages themselves, and a confusing array of descriptions and names being used for all of these. Several years ago, there were basically two options on the table, 3D-ICs and 2.5D. But as chipmakers began understanding the difficulty, cost and reduced benef... » read more

Embedded Die Packaging Emerges

By Mark LaPedus - 09 Apr, 2018 - Comments: 1

Embedded die packaging is seeing renewed demand amid the push towards chips and systems that require smaller form factors. ASE, AT&S, GE, Shinko, Taiyo Yuden, TDK, Würth Elektronik and others compete in the merchant embedded die packaging market, according to Yole Développement. In fact, ASE and TDK have a joint venture in the arena, which is beginning to ramp up production. Additional... » read more

Fan-Out Wars Begin

By Mark LaPedus - 05 Feb, 2018 - Comments: 3

Several packaging houses are developing the next wave of high-density fan-out packages for premium smartphones, but perhaps a bigger battle is brewing in the lower density fan-out arena. Amkor, ASE, STATS ChipPAC and others sell traditional low-density fan-out packages, although some new and competitive technologies are beginning to appear in the market. Low-density fan-out, or sometimes cal... » read more

Advanced Packaging Picks Up Steam

By Jeff Dorsch - 10 Jul, 2017 - Comments: 0

The semiconductor industry’s push toward continued miniaturization and increasing complexity is driving wider adoption of system-in-package (SiP) technology. One of the big benefits of [getkc id="199" kc_name="SiP"] is that it allows more features to be squeezed into ever-smaller form factors, such as wearable gadgets and medical implants. So while the individual chips in this package may ... » read more

Shrink Or Package?

By Ed Sperling - 19 Jun, 2017 - Comments: 0

Advanced packaging is rapidly becoming a mainstream option for chipmakers as the cost of integrating heterogeneous components on a single die continues to rise. Despite several years of buzz around this shift, the reality is that it has taken more than a half-century to materialize. Advanced [getkc id="27" kc_name="packaging"] began with IBM flip chips in the 1960s, and it got another boost ... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?