tag: Tensilica

Roundtable: Battery Life Vs. Delay
By Ed Sperling - 16 Jan, 2013 - Comments: 0

Low-Power High-Performance Engineering talks about the challenges of dealing with latency in semiconductor design with Andrew Caples of Mentor Graphics, Chris Rowen of Tensilica, Drew Wingard of Sonics and Larry Hudepohl of MIPS Technologies. [youtube vid=Q_opQ3W9esA] » read more

Executive Outlook
By Ed Sperling - 19 Dec, 2012 - Comments: 0

By Ed Sperling The view from the top of companies is a like a high-level of abstraction for viewing the industry. While engineers get caught up in individual projects, or pieces of projects, CEOs and CTOs tend to see things from a much broader perspective. So what do they see as the big issues and developments over the next 12 to 24 months? System-Level Design asked industry leaders that q... » read more

Virtual IDM Progress Report
By Ed Sperling - 06 Dec, 2012 - Comments: 0

By Ed Sperling Complexity, tight power budgets, disaggregation of the supply chain and market fragmentation are conspiring to force much tighter partnerships among companies that develop different pieces of an SoC, as well as those that collaborate on even larger systems. This confluence of factors has forced the rules for how companies work together to be rewritten, but even within that frame... » read more

The Growing Integration Challenge
By Ed Sperling - 08 Nov, 2012 - Comments: 0

By Ed Sperling As the number of processors and the amount of memory and IP on a chip continues to skyrocket, so does the challenge for integrating all of this stuff on a single die—or even multiple dies in the same package. There are a number of reasons why it’s getting more difficult to make all of these IP blocks work together. First of all, nothing ever stands still in design. As a r... » read more

CPU Architectures Get Specific
By Ed Sperling - 11 Oct, 2012 - Comments: 0

By Ann Steffora Mutschler SoC and system design is already complicated, but as complexity continues to rise the industry must determine how to maintain sensitivity to power and cost and performance in the CPU architecture. Where does this stand today—not just with architectures and microarchitectures for consumer electronics but all other kinds of applications? What kinds of changes... » read more

The Increasing Challenge Of Reducing Latency
By Ed Sperling - 11 Oct, 2012 - Comments: 0

By Ed Sperling When the first mainframe computers were introduced the big challenge was to improve performance by decreasing the latency between spinning reels of tape and the processor—while also increasing the speed at which the processor could crunch ones and zeroes. Fast forward more than six decades and the two issues are now blurred and often confused. Latency is still a drag on per... » read more

Your Job is Harder Than Mine
By Ann Mutschler - 11 Oct, 2012 - Comments: 0

What I do for a living is listen – a lot – and try to make sense of the myriad challenges that I hear about in terms of design and managing power and performance. What you do as an architect, design engineer or verification engineer is live in the trenches with it all, every day. I admire and respect that. This is especially true as I recently pondered and talked with industry luminaries... » read more

The Good And Bad Of Models
By Ed Sperling - 27 Sep, 2012 - Comments: 0

By Ann Steffora Mutschler Driven by fierce competition and the fact that socket decisions are made long before silicon is manufactured, semiconductor companies today ship models and virtual prototypes to their OEMs very early in hopes of locking in the socket. Admittedly, this has been happening for some time, but due to complexity and the need for flexibility of models and virtual platf... » read more

Keeping The Balance
By Ed Sperling - 13 Sep, 2012 - Comments: 0

By Ann Steffora Mutschler The brains of datacenters today are more powerful than ever due to technology advancements in chip architectures and in manufacturing processes that allow more processing power thanks to Moore’s Law. But knowing exactly how and where to configure the processors and cores for optimum throughput and performance within a certain power budget raises a number of qu... » read more

Blurring The Lines At The OS Level
By Ed Sperling - 13 Sep, 2012 - Comments: 0

By Ed Sperling Picking an operating system—or choosing not to use an operating system—is becoming as complex a decision as choosing which IP to use in an SoC. Even decisions that sound straightforward may have ramifications on the total system power budget or performance, requiring them to be an integral part of the overall architectural process. But the choice of operating systems, as ... » read more

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