A Lightweight Scan Instrumentation For Enhancing The Post-Silicon Test Efficiency in ICs (U. of Florida)


A technical paper titled "Enhancing Test Efficiency through Automated ATPG-Aware Lightweight Scan Instrumentation" was published by researchers at University of Florida. Abstract "Scan-based Design-for-Testability (DFT) measures are prevalent in modern digital integrated circuits to achieve high test quality at low hardware cost. With the advent of 3D heterogeneous integration and chiplet-b... » read more

IP To Meet 2.5D Requirements


The semiconductor industry is still in the early stages of evolution in the realm of 2.5D, but when these devices do come out, the IP used on them will have to be brand new, according to Javier DeLaCruz, senior director of engineering at eSilicon. “The IP causes the biggest risk that you’re going to have in this implementation,” he said. “Everything else in here for making those ASIC... » read more