Speeding Up AI

By Ed Sperling - 06 Jun, 2019 - Comments: 0

Robert Blake, president and CEO of Achronix, sat down with Semiconductor Engineering to talk about AI, which processors work best where, and different approaches to accelerate performance. SE: How is AI affecting the FPGA business, given the constant changes in algorithms and the proliferation of AI almost everywhere? Blake: As we talk to more and more customers deploying new products and... » read more

Inferencing At The Edge

By Ed Sperling - 04 Jun, 2019 - Comments: 0

Geoff Tate, CEO of Flex Logix, talks about the challenges of power and performance at the edge, why this market is so important from a business and technology standpoint, and what factors need to be balanced. » read more

New Challenges For Data Centers

By Ed Sperling - 08 May, 2019 - Comments: 0

Rita Horner, senior technical marketing manager in Synopsys’ Solutions Group, looks at the impact of a significant rise in data, why this often leads to big cost increases, and where the bottlenecks are occurring. » read more

The Promise Of GDDR6 And 7nm

By Frank Ferro - 14 Feb, 2019 - Comments: 1

Research Nester, a market research and consulting firm, estimates that the “global market of computer graphics may witness a remarkable growth and reach at the valuation of $215.5 billion by the end of year 2024.” Plus, it says this market is expected to grow at a significant compound annual growth rate or CAGR of 6.1% over the forecast period 2017 to 2024. Computer graphics is just the ... » read more

Designing Networking Chips

By Ed Sperling - 07 Feb, 2019 - Comments: 0

Susheel Tadikonda, vice president of networking and storage at Synopsys, talks about what’s changed in the way networking chips are being designed to deal with a massive increase in data. One of those shifts involves software-defined networking, where the greatest complexity resides in the software. That also has a big impact on the entire design flow, from pre-silicon to post-silicon. htt... » read more

Benchmarks For The Edge

By Ed Sperling - 07 Feb, 2019 - Comments: 0

Geoff Tate, CEO of Flex Logix, talks about benchmarking in edge devices, particularly for convolutional neural networks. https://youtu.be/-beVEpKAM4M » read more

Edge Inferencing Challenges

By Ed Sperling - 10 Jan, 2019 - Comments: 0

Geoff Tate, CEO of Flex Logix, talks about balancing different variables to improve performance and reduce power at the lowest cost possible in order to do inferencing in edge devices. https://youtu.be/1BTxwew--5U » read more

The Long Pause

By Ed Sperling - 07 Jun, 2018 - Comments: 0

Carmakers are leaping over each other to roll out cars that meet SAE Level 3 requirements, whereby under some conditions drivers can let go of the steering wheel. Getting to Level 5 will take a lot longer, and there is some debate about where and even whether Level 4 will ever happen (see Fig. 1). Fig. 1: Levels of autonomy. Source: Auto Alliance There are two big gaps that need to be a... » read more

Tech Talk: HBM vs. GDDR6

By Ed Sperling - 10 May, 2018 - Comments: 0

Frank Ferro, senior director of product management at Rambus, talks about memory bottlenecks and why both GDDR6 and high-bandwidth memory are gaining steam and for which markets. https://youtu.be/CPqdZZooS2g Related Video GDDR6 – HBM2 Tradeoffs (2019) What type of DRAM works best where. » read more

The Ideal Solution For AI Applications — Speedcore eFPGAs

By Achronix - 04 Apr, 2018 - Comments: 0

AI requires a careful balance of datapath performance, memory latency, and throughput that requires an approach based on pulling as much of the functionality as possible into an ASIC or SoC. But that single-chip device needs plasticity to be able to handle the changes in structure that are inevitable in machine-learning projects. Adding eFPGA technology provides the mixture of flexibility and s... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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