NAND Flash Targets 1,000 Layers

By Bryon Moyer - 04 Dec, 2024 - Comments: 0

The chip industry is pushing to quadruple the stack height of 3D NAND flash from 200 layers to 800 layers or more over the next few years, using the additional capacity will help to feed the unending need for more memory of all types. Those additional layers will add new reliability issues a number of incremental reliability challenges, but the NAND flash industry has been steadily increasin... » read more

3D NAND’s Vertical Scaling Race

By Mark LaPedus - 17 Dec, 2020 - Comments: 1

3D NAND suppliers are accelerating their efforts to move to the next technology nodes in a race against growing competition, but all of these vendors are facing an assortment of new business, manufacturing, and cost challenges. Two suppliers, Micron and SK Hynix, recently leapfrogged the competition and have taken the scaling race lead in 3D NAND. But Samsung and the Kioxia-Western Digital (... » read more

The Week In Review: Manufacturing

By Mark LaPedus - 20 May, 2016 - Comments: 0

Chipmakers IC Insights released its top chip makers in terms of sales for the first quarter of 2016. The top-20 ranking includes three pure-play foundries (TSMC, GlobalFoundries, and UMC) and six fabless companies. Intel remained in the top spot, followed in order by Samsung and TSMC. The biggest movers in the ranking were made by the new Broadcom (Avago/Broadcom) and Nvidia. Broadcom jumped f... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

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The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

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Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

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NAND Flash Targets 1,000 Layers

3D NAND’s Vertical Scaling Race

The Week In Review: Manufacturing