tag: TSI Semiconductor

Chip Industry Week In Review

By The SE Staff - 26 Sep, 2025 - Comments: 0

U.S. Trade Representative Jamieson Greer warned Southeast Asian semiconductor manufacturers that they must shift production to the U.S. or face new punitive tariffs, reports the South China Morning Post. President Trump previously floated a 100% tariff on imported chips. Malaysia and other regional economies are offering large concessions and promises of U.S. goods purchases in hopes of securin... » read more

The Week In Review: Design

By Ed Sperling - 05 Sep, 2014 - Comments: 0

Tools Mentor Graphics unveiled a hypervisor with configuration, debugging and hardware support. The solution is aimed at a variety of vertical markets, ranging from industrial and medical to consumer electronics. NXP uncorked a passive Inter-Integrated Circuit (I²C) solution for near-field communications tagging, allowing appliances, wearables and consumer electronics to use existing NFC-... » read more

Trending Articles

The Sub-2nm Paradox

Reducing variation in manufacturing, monitoring behavior over time, and targeting specific workloads can have a big impact on power, performance, and area/cost.

AI Accelerator Testing Depends On DFT Innovations

Multi-die assemblies greatly increase the number of things that can go wrong, and the difficulty of finding them.

by Laura Peters

Flash Getting Stacked High-Bandwidth Version

Inspired by HBM, HBF could improve AI efficiency in 3D flash memory.

Chiplets Need A New Workflow

Multi-die assemblies are facing full system-level challenges, but engineering teams need coordinated and repeatable ways to identify risks early and scale reliably.

by Ann Mutschler

Chip Industry Week In Review

Taiwan, Europe packaging buildout; 2nm ramps; quantum big $; 2 new university hubs; agent honeypots; Samsung strike averted; extreme environment chip design; quantum-dot qubit device fabricated w/high-NA EUV; EU flagship power electronics project; CNTs.

by The SE Staff

Knowledge Centers
Entities, people and technologies explored

Related Articles

Can A Computer Science Student Be Taught To Design Hardware?

To fill the talent gap, CS majors could be taught to design hardware, and the EE curriculum could be adapted or even shortened.

by Liz Allan

Advanced Packaging Limits Come Into Focus

Mechanical and process control limits are now shaping what can be manufactured at scale.

by Gregory Haley

Startup Funding: Q1 2026

Massive rounds for AI, EDA, and manufacturing; 80 startups raise $8.4B.

by Jesse Allen

All AI Data Center Interconnects Will Be Optical Within 5 Years

InP and SiPho join CMOS as critical technologies. Lasers, CPO and OCS will be everywhere (indium phosphide, silicon photonics, co-packaged optics, optical circuit switch).

by Geoff Tate

Making Hybrid Bonding Better

Why this technology is so essential for multi-die assemblies, and how it can be improved.

by Laura Peters

When Semiconductor Materials Misbehave

The gap between lab performance and fab reality is growing wider as packages grow more complex.

by Gregory Haley

Backside Power Delivery Creates Fab Tool, Thermal Dissipation Barriers

Moving the power delivery network to the backside of a chip reduces congestion, but it introduces new challenges for fabs.

by Laura Peters

Securing Hardware For The Quantum Era

Quantum computers may become a security threat as early as next year, and that threat will continue to grow over the next several years.

by Ann Mutschler

About

Navigation

Connect With Us

Facebook
Twitter @semiEngineering
LinkedIn
YouTube

Copyright ©2013-2026 SMG | Terms of Service | Privacy Policy